From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: "Jingoo Han" To: "'Jisheng Zhang'" , , References: <20170718064821.3668-1-jszhang@marvell.com> In-Reply-To: <20170718064821.3668-1-jszhang@marvell.com> Subject: Re: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not Date: Tue, 18 Jul 2017 23:25:24 -0400 Message-ID: <000001d3003e$a9ad0fe0$fd072fa0$@gmail.com> MIME-Version: 1.0 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote: > > The ATU CTRL2 register is 32 bit, besides the enable bit, other bits > may also be set. To check whether the ATU is enabled or not, we should > test the enable bit. > > Signed-off-by: Jisheng Zhang > Acked-by: Joao Pinto Acked-by: Jingoo Han Best regards, Jingoo Han > --- > Since v1: > - Add Joao's Ack > - Fix typo in commit msg, thank Jingoo > > drivers/pci/dwc/pcie-designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie- > designware.c > index 0e03af279259..6bf0b409050a 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > int index, int type, > */ > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) > { > val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); > - if (val == PCIE_ATU_ENABLE) > + if (val & PCIE_ATU_ENABLE) > return; > > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); > -- > 2.13.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: jingoohan1@gmail.com (Jingoo Han) Date: Tue, 18 Jul 2017 23:25:24 -0400 Subject: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not In-Reply-To: <20170718064821.3668-1-jszhang@marvell.com> References: <20170718064821.3668-1-jszhang@marvell.com> Message-ID: <000001d3003e$a9ad0fe0$fd072fa0$@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote: > > The ATU CTRL2 register is 32 bit, besides the enable bit, other bits > may also be set. To check whether the ATU is enabled or not, we should > test the enable bit. > > Signed-off-by: Jisheng Zhang > Acked-by: Joao Pinto Acked-by: Jingoo Han Best regards, Jingoo Han > --- > Since v1: > - Add Joao's Ack > - Fix typo in commit msg, thank Jingoo > > drivers/pci/dwc/pcie-designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie- > designware.c > index 0e03af279259..6bf0b409050a 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > int index, int type, > */ > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) > { > val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); > - if (val == PCIE_ATU_ENABLE) > + if (val & PCIE_ATU_ENABLE) > return; > > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); > -- > 2.13.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752672AbdGSDZ3 (ORCPT ); Tue, 18 Jul 2017 23:25:29 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:35680 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751906AbdGSDZ1 (ORCPT ); Tue, 18 Jul 2017 23:25:27 -0400 From: "Jingoo Han" To: "'Jisheng Zhang'" , , Cc: , , References: <20170718064821.3668-1-jszhang@marvell.com> In-Reply-To: <20170718064821.3668-1-jszhang@marvell.com> Subject: Re: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not Date: Tue, 18 Jul 2017 23:25:24 -0400 Message-ID: <000001d3003e$a9ad0fe0$fd072fa0$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQJswy8xm5l/YDiRsCKULJxirEprvqEm9q3A Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote: > > The ATU CTRL2 register is 32 bit, besides the enable bit, other bits > may also be set. To check whether the ATU is enabled or not, we should > test the enable bit. > > Signed-off-by: Jisheng Zhang > Acked-by: Joao Pinto Acked-by: Jingoo Han Best regards, Jingoo Han > --- > Since v1: > - Add Joao's Ack > - Fix typo in commit msg, thank Jingoo > > drivers/pci/dwc/pcie-designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie- > designware.c > index 0e03af279259..6bf0b409050a 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > int index, int type, > */ > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) > { > val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); > - if (val == PCIE_ATU_ENABLE) > + if (val & PCIE_ATU_ENABLE) > return; > > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); > -- > 2.13.2