From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jingoo Han" Subject: Re: [RESEND PATCH v6 14/27] drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll Date: Mon, 23 Apr 2018 21:25:56 -0400 Message-ID: <000001d3db6b$32a87200$97f95600$@gmail.com> References: <20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-15-enric.balletbo@collabora.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180423105003.9004-15-enric.balletbo@collabora.com> Content-Language: en-us List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: 'Enric Balletbo i Serra' , architt@codeaurora.org, inki.dae@samsung.com, thierry.reding@gmail.com, hjc@rock-chips.com, seanpaul@chromium.org, airlied@linux.ie, tfiga@chromium.org, heiko@sntech.de Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Laurent.pinchart@ideasonboard.com, kernel@collabora.com, m.szyprowski@samsung.com, linux-samsung-soc@vger.kernel.org, rydberg@bitmath.org, krzk@kernel.org, linux-rockchip@lists.infradead.org, kgene@kernel.org, orjan.eide@arm.com, wxt@rock-chips.com, jeffy.chen@rock-chips.com, linux-arm-kernel@lists.infradead.org, wzz@rock-chips.com, hl@rock-chips.com, sw0312.kim@samsung.com, dianders@chromium.org, kyungmin.park@samsung.com, kuankuan.y@gmail.com, hshi@chromium.org List-Id: linux-rockchip.vger.kernel.org T24gTW9uZGF5LCBBcHJpbCAyMywgMjAxOCA2OjUwIEFNLCBFbnJpYyBCYWxsZXRibyBpIFNlcnJh IHdyb3RlOgo+IAo+IEZyb206IHphaW4gd2FuZyA8d3p6QHJvY2stY2hpcHMuY29tPgo+IAo+IFRo ZXJlIGlzIG5vIHJlZ2lzdGVyIG5hbWVkIEFOQUxPR0lYX0RQX1BMTF9DVEwgaW4gUm9ja2NoaXAg ZWRwIHBoeSByZWcKPiBsaXN0LiAgV2Ugc2hvdWxkIHVzZSBCSVRfNCBpbiBBTkFMT0dJWF9EUF9Q RCB0byBjb250cm9sIHRoZSBwbGwgcG93ZXIKPiBpbnN0ZWFkIG9mIEFOQUxPR0lYX0RQX1BMTF9D VEwuCj4gCj4gQ2M6IERvdWdsYXMgQW5kZXJzb24gPGRpYW5kZXJzQGNocm9taXVtLm9yZz4KPiBT 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<20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-15-enric.balletbo@collabora.com> Message-ID: <000001d3db6b$32a87200$97f95600$@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Monday, April 23, 2018 6:50 AM, Enric Balletbo i Serra wrote: > > From: zain wang > > There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg > list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power > instead of ANALOGIX_DP_PLL_CTL. > > Cc: Douglas Anderson > Signed-off-by: zain wang > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Reviewed-by: Andrzej Hajda > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > Reviewed-by: Archit Taneja Acked-by: Jingoo Han Best regards, Jingoo Han > --- > > .../gpu/drm/bridge/analogix/analogix_dp_reg.c | 20 +++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index 7b7fd227e1f9..02ab1aaa9993 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -230,16 +230,20 @@ enum pll_status > analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) > void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool > enable) > { > u32 reg; > + u32 mask = DP_PLL_PD; > + u32 pd_addr = ANALOGIX_DP_PLL_CTL; > > - if (enable) { > - reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); > - reg |= DP_PLL_PD; > - writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); > - } else { > - reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); > - reg &= ~DP_PLL_PD; > - writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { > + pd_addr = ANALOGIX_DP_PD; > + mask = RK_PLL_PD; > } > + > + reg = readl(dp->reg_base + pd_addr); > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + pd_addr); > } > > void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, > -- > 2.17.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932726AbeDXB0C (ORCPT ); Mon, 23 Apr 2018 21:26:02 -0400 Received: from mail-qk0-f195.google.com ([209.85.220.195]:41824 "EHLO mail-qk0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932633AbeDXB0A (ORCPT ); Mon, 23 Apr 2018 21:26:00 -0400 X-Google-Smtp-Source: AB8JxZriHF8qYh7IGOZlVX8FilAZfCmAsQSjvmxtdq89pQdYSe/r27tRRcLrl/btWWbvaXn/ehcSFQ== From: "Jingoo Han" To: "'Enric Balletbo i Serra'" , , , , , , , , Cc: , , , , , , , , , , , , , , , , , , , , , , References: <20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-15-enric.balletbo@collabora.com> In-Reply-To: <20180423105003.9004-15-enric.balletbo@collabora.com> Subject: Re: [RESEND PATCH v6 14/27] drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll Date: Mon, 23 Apr 2018 21:25:56 -0400 Message-ID: <000001d3db6b$32a87200$97f95600$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQJsKqzGdLQ3B8H319FIYPcigFOt/AGILm3RotI/UVA= Content-Language: en-us Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday, April 23, 2018 6:50 AM, Enric Balletbo i Serra wrote: > > From: zain wang > > There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg > list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power > instead of ANALOGIX_DP_PLL_CTL. > > Cc: Douglas Anderson > Signed-off-by: zain wang > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Reviewed-by: Andrzej Hajda > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > Reviewed-by: Archit Taneja Acked-by: Jingoo Han Best regards, Jingoo Han > --- > > .../gpu/drm/bridge/analogix/analogix_dp_reg.c | 20 +++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index 7b7fd227e1f9..02ab1aaa9993 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -230,16 +230,20 @@ enum pll_status > analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) > void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool > enable) > { > u32 reg; > + u32 mask = DP_PLL_PD; > + u32 pd_addr = ANALOGIX_DP_PLL_CTL; > > - if (enable) { > - reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); > - reg |= DP_PLL_PD; > - writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); > - } else { > - reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); > - reg &= ~DP_PLL_PD; > - writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { > + pd_addr = ANALOGIX_DP_PD; > + mask = RK_PLL_PD; > } > + > + reg = readl(dp->reg_base + pd_addr); > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + pd_addr); > } > > void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, > -- > 2.17.0