diff for duplicates of <000201d37a7b$0fa31b30$2ee95190$@gmail.com> diff --git a/a/1.txt b/N1/1.txt index cdc2a54..9e4b076 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,16 +1,13 @@ On Wednesday, December 20, 2017 2:19 PM, Joao Pinto wrote: ->=20 ->=20 +> +> > Hi, ->=20 -> =C3=80s 11:29 PM de 12/19/2017, Niklas Cassel escreveu: -> > Certain registers that pcie-designware-ep tries to write to are = -read- +> +> Às 11:29 PM de 12/19/2017, Niklas Cassel escreveu: +> > Certain registers that pcie-designware-ep tries to write to are read- > only -> > registers. However, these registers can become read/write if we = -first -> > enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit = -before/after +> > registers. However, these registers can become read/write if we first +> > enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit before/after > > writing these registers. > > > > Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> @@ -23,12 +20,11 @@ before/after > > index c92ab87fd660..3fb34be99715 100644 > > --- a/drivers/pci/dwc/pcie-designware-ep.c > > +++ b/drivers/pci/dwc/pcie-designware-ep.c -> > @@ -35,8 +35,10 @@ static void dw_pcie_ep_reset_bar(struct dw_pcie = -*pci, +> > @@ -35,8 +35,10 @@ static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, > enum pci_barno bar) > > u32 reg; > > -> > reg =3D PCI_BASE_ADDRESS_0 + (4 * bar); +> > reg = PCI_BASE_ADDRESS_0 + (4 * bar); > > + dw_pcie_dbi_ro_wr_en(pci); > > dw_pcie_writel_dbi2(pci, reg, 0x0); > > dw_pcie_writel_dbi(pci, reg, 0x0); @@ -36,17 +32,15 @@ before/after > > } > > > > static int dw_pcie_ep_write_header(struct pci_epc *epc, -> > @@ -45,6 +47,7 @@ static int dw_pcie_ep_write_header(struct pci_epc = -*epc, -> > struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); -> > struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); +> > @@ -45,6 +47,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, +> > struct dw_pcie_ep *ep = epc_get_drvdata(epc); +> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > > > > + dw_pcie_dbi_ro_wr_en(pci); > > dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid); > > dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid); > > dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid); -> > @@ -58,6 +61,7 @@ static int dw_pcie_ep_write_header(struct pci_epc = -*epc, +> > @@ -58,6 +61,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, > > dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id); > > dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN, > > hdr->interrupt_pin); @@ -54,8 +48,7 @@ before/after > > > > return 0; > > } -> > @@ -142,8 +146,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc = -*epc, +> > @@ -142,8 +146,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, > enum pci_barno bar, > > if (ret) > > return ret; @@ -67,12 +60,11 @@ before/after > > > > return 0; > > } -> > @@ -223,7 +229,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc = -*epc, +> > @@ -223,7 +229,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, > u8 encode_int) -> > val =3D dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); -> > val &=3D ~MSI_CAP_MMC_MASK; -> > val |=3D (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; +> > val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); +> > val &= ~MSI_CAP_MMC_MASK; +> > val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; > > + dw_pcie_dbi_ro_wr_en(pci); > > dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); > > + dw_pcie_dbi_ro_wr_dis(pci); @@ -80,7 +72,7 @@ before/after > > return 0; > > } > > ->=20 +> > Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> diff --git a/a/content_digest b/N1/content_digest index 0f1a328..4feeee5 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -14,18 +14,15 @@ "\00:1\0" "b\0" "On Wednesday, December 20, 2017 2:19 PM, Joao Pinto wrote:\n" - ">=20\n" - ">=20\n" + "> \n" + "> \n" "> Hi,\n" - ">=20\n" - "> =C3=80s 11:29 PM de 12/19/2017, Niklas Cassel escreveu:\n" - "> > Certain registers that pcie-designware-ep tries to write to are =\n" - "read-\n" + "> \n" + "> \303\200s 11:29 PM de 12/19/2017, Niklas Cassel escreveu:\n" + "> > Certain registers that pcie-designware-ep tries to write to are read-\n" "> only\n" - "> > registers. However, these registers can become read/write if we =\n" - "first\n" - "> > enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit =\n" - "before/after\n" + "> > registers. However, these registers can become read/write if we first\n" + "> > enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit before/after\n" "> > writing these registers.\n" "> >\n" "> > Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>\n" @@ -38,12 +35,11 @@ "> > index c92ab87fd660..3fb34be99715 100644\n" "> > --- a/drivers/pci/dwc/pcie-designware-ep.c\n" "> > +++ b/drivers/pci/dwc/pcie-designware-ep.c\n" - "> > @@ -35,8 +35,10 @@ static void dw_pcie_ep_reset_bar(struct dw_pcie =\n" - "*pci,\n" + "> > @@ -35,8 +35,10 @@ static void dw_pcie_ep_reset_bar(struct dw_pcie *pci,\n" "> enum pci_barno bar)\n" "> > \tu32 reg;\n" "> >\n" - "> > \treg =3D PCI_BASE_ADDRESS_0 + (4 * bar);\n" + "> > \treg = PCI_BASE_ADDRESS_0 + (4 * bar);\n" "> > +\tdw_pcie_dbi_ro_wr_en(pci);\n" "> > \tdw_pcie_writel_dbi2(pci, reg, 0x0);\n" "> > \tdw_pcie_writel_dbi(pci, reg, 0x0);\n" @@ -51,17 +47,15 @@ "> > }\n" "> >\n" "> > static int dw_pcie_ep_write_header(struct pci_epc *epc,\n" - "> > @@ -45,6 +47,7 @@ static int dw_pcie_ep_write_header(struct pci_epc =\n" - "*epc,\n" - "> > \tstruct dw_pcie_ep *ep =3D epc_get_drvdata(epc);\n" - "> > \tstruct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);\n" + "> > @@ -45,6 +47,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc,\n" + "> > \tstruct dw_pcie_ep *ep = epc_get_drvdata(epc);\n" + "> > \tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n" "> >\n" "> > +\tdw_pcie_dbi_ro_wr_en(pci);\n" "> > \tdw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);\n" "> > \tdw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);\n" "> > \tdw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);\n" - "> > @@ -58,6 +61,7 @@ static int dw_pcie_ep_write_header(struct pci_epc =\n" - "*epc,\n" + "> > @@ -58,6 +61,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc,\n" "> > \tdw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);\n" "> > \tdw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,\n" "> > \t\t\t hdr->interrupt_pin);\n" @@ -69,8 +63,7 @@ "> >\n" "> > \treturn 0;\n" "> > }\n" - "> > @@ -142,8 +146,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc =\n" - "*epc,\n" + "> > @@ -142,8 +146,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc,\n" "> enum pci_barno bar,\n" "> > \tif (ret)\n" "> > \t\treturn ret;\n" @@ -82,12 +75,11 @@ "> >\n" "> > \treturn 0;\n" "> > }\n" - "> > @@ -223,7 +229,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc =\n" - "*epc,\n" + "> > @@ -223,7 +229,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc,\n" "> u8 encode_int)\n" - "> > \tval =3D dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);\n" - "> > \tval &=3D ~MSI_CAP_MMC_MASK;\n" - "> > \tval |=3D (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;\n" + "> > \tval = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);\n" + "> > \tval &= ~MSI_CAP_MMC_MASK;\n" + "> > \tval |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;\n" "> > +\tdw_pcie_dbi_ro_wr_en(pci);\n" "> > \tdw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);\n" "> > +\tdw_pcie_dbi_ro_wr_dis(pci);\n" @@ -95,7 +87,7 @@ "> > \treturn 0;\n" "> > }\n" "> >\n" - ">=20\n" + "> \n" "> Acked-by: Joao Pinto <jpinto@synopsys.com>\n" "\n" "Acked-by: Jingoo Han <jingoohan1@gmail.com>\n" @@ -103,4 +95,4 @@ "Best regards,\n" Jingoo Han -8cb0e38be3d0011a1cfa6301b9cfb8cd78942d497978c250254bff0d2075b816 +606d70d03305573421b552eac12688f6f0318658f22208052d7f22abd5c0f3f1
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.