From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jingoo Han" Subject: Re: [RESEND PATCH v6 10/27] drm/bridge: analogix_dp: Check dpcd write/read status Date: Tue, 24 Apr 2018 09:54:04 -0400 Message-ID: <000201d3dbd3$b70de580$2529b080$@gmail.com> References: <20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-11-enric.balletbo@collabora.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180423105003.9004-11-enric.balletbo@collabora.com> Content-Language: en-us List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: 'Enric Balletbo i Serra' , architt@codeaurora.org, inki.dae@samsung.com, thierry.reding@gmail.com, hjc@rock-chips.com, seanpaul@chromium.org, airlied@linux.ie, tfiga@chromium.org, heiko@sntech.de Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Laurent.pinchart@ideasonboard.com, "'Kristian H . Kristensen'" , kernel@collabora.com, m.szyprowski@samsung.com, linux-samsung-soc@vger.kernel.org, rydberg@bitmath.org, krzk@kernel.org, linux-rockchip@lists.infradead.org, kgene@kernel.org, orjan.eide@arm.com, wxt@rock-chips.com, jeffy.chen@rock-chips.com, linux-arm-kernel@lists.infradead.org, wzz@rock-chips.com, hl@rock-chips.com, sw0312.kim@samsung.com, dianders@chromium.org, kyungmin.park@samsung.com, kuankuan.y@gmail.com, hshi@chromium.org List-Id: linux-rockchip.vger.kernel.org T24gTW9uZGF5LCBBcHJpbCAyMywgMjAxOCA2OjUwIEFNLCBFbnJpYyBCYWxsZXRibyBpIFNlcnJh IHdyb3RlOgo+IAo+IEZyb206IExpbiBIdWFuZyA8aGxAcm9jay1jaGlwcy5jb20+Cj4gCj4gV2Ug bmVlZCB0byBjaGVjayB0aGUgZHBjZCB3cml0ZS9yZWFkIHJldHVybiB2YWx1ZSB0byBzZWUgd2hl dGhlciB0aGUKPiB3cml0ZS9yZWFkIHdhcyBzdWNjZXNzZnVsCj4gCj4gQ2M6IEtyaXN0aWFuIEgu IEtyaXN0ZW5zZW4gPGhvZWdzYmVyZ0BjaHJvbWl1bS5vcmc+Cj4gU2lnbmVkLW9mZi1ieTogTGlu IEh1YW5nIDxobEByb2NrLWNoaXBzLmNvbT4KPiBTaWduZWQtb2ZmLWJ5OiB6YWluIHdhbmcgPHd6 ekByb2NrLWNoaXBzLmNvbT4KPiBTaWduZWQtb2ZmLWJ5OiBEb3VnbGFzIEFuZGVyc29uIDxkaWFu ZGVyc0BjaHJvbWl1bS5vcmc+Cj4gU2lnbmVkLW9mZi1ieTogU2VhbiBQYXVsIDxzZWFucGF1bEBj aHJvbWl1bS5vcmc+Cj4gU2lnbmVkLW9mZi1ieTogVGhpZXJyeSBFc2NhbmRlIDx0aGllcnJ5LmVz Y2FuZGVAY29sbGFib3JhLmNvbT4KPiBSZXZpZXdlZC1ieTogQW5kcnplaiBIYWpkYSA8YS5oYWpk YUBzYW1zdW5nLmNvbT4KPiBTaWduZWQtb2ZmLWJ5OiBFbnJpYyBCYWxsZXRibyBpIFNlcnJhIDxl bnJpYy5iYWxsZXRib0Bjb2xsYWJvcmEuY29tPgo+IFRlc3RlZC1ieTogTWFyZWsgU3p5cHJvd3Nr aSA8bS5zenlwcm93c2tpQHNhbXN1bmcuY29tPgo+IFJldmlld2VkLWJ5OiBBcmNoaXQgVGFuZWph IDxhcmNoaXR0QGNvZGVhdXJvcmEub3JnPgoKQWNrZWQtYnk6IEppbmdvbyBIYW4gPGppbmdvb2hh bjFAZ21haWwuY29tPgoKQmVzdCByZWdhcmRzLApKaW5nb28gSGFuCgo+IC0tLQo+IAo+ICAuLi4v ZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9jb3JlLmMgICAgfCAxNjkgKysrKysrKysr KysrKy0tLS0tCj4gIDEgZmlsZSBjaGFuZ2VkLCAxMjcgaW5zZXJ0aW9ucygrKSwgNDIgZGVsZXRp b25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgv YW5hbG9naXhfZHBfY29yZS5jCj4gYi9kcml2ZXJzL2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2Fu YWxvZ2l4X2RwX2NvcmUuYwo+IGluZGV4IDFlMTc0M2I1OWM3Ny4uNzVlNjFlYmY2NzIyIDEwMDY0 NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfY29y ZS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9j b3JlLmMKPiBAQCAtMTYwLDgwICsxNjAsMTM3IEBAIGludCBhbmFsb2dpeF9kcF9kaXNhYmxlX3Bz cihzdHJ1Y3QKPiBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+ICB9Cj4gIEVYUE9SVF9TWU1CT0xf R1BMKGFuYWxvZ2l4X2RwX2Rpc2FibGVfcHNyKTsKPiAKPiAtc3RhdGljIGJvb2wgYW5hbG9naXhf ZHBfZGV0ZWN0X3NpbmtfcHNyKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+ICtzdGF0 aWMgaW50IGFuYWxvZ2l4X2RwX2RldGVjdF9zaW5rX3BzcihzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2 aWNlICpkcCkKPiAgewo+ICAJdW5zaWduZWQgY2hhciBwc3JfdmVyc2lvbjsKPiArCWludCByZXQ7 Cj4gKwo+ICsJcmV0ID0gZHJtX2RwX2RwY2RfcmVhZGIoJmRwLT5hdXgsIERQX1BTUl9TVVBQT1JU LCAmcHNyX3ZlcnNpb24pOwo+ICsJaWYgKHJldCAhPSAxKSB7Cj4gKwkJZGV2X2VycihkcC0+ZGV2 LCAiZmFpbGVkIHRvIGdldCBQU1IgdmVyc2lvbiwgZGlzYWJsZSBpdFxuIik7Cj4gKwkJcmV0dXJu IHJldDsKPiArCX0KPiAKPiAtCWRybV9kcF9kcGNkX3JlYWRiKCZkcC0+YXV4LCBEUF9QU1JfU1VQ UE9SVCwgJnBzcl92ZXJzaW9uKTsKPiAgCWRldl9kYmcoZHAtPmRldiwgIlBhbmVsIFBTUiB2ZXJz aW9uIDogJXhcbiIsIHBzcl92ZXJzaW9uKTsKPiAKPiAtCXJldHVybiAocHNyX3ZlcnNpb24gJiBE UF9QU1JfSVNfU1VQUE9SVEVEKSA/IHRydWUgOiBmYWxzZTsKPiArCWRwLT5wc3JfZW5hYmxlID0g KHBzcl92ZXJzaW9uICYgRFBfUFNSX0lTX1NVUFBPUlRFRCkgPyB0cnVlIDogZmFsc2U7Cj4gKwo+ ICsJcmV0dXJuIDA7Cj4gIH0KPiAKPiAtc3RhdGljIHZvaWQgYW5hbG9naXhfZHBfZW5hYmxlX3Np bmtfcHNyKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+ICtzdGF0aWMgaW50IGFuYWxv Z2l4X2RwX2VuYWJsZV9zaW5rX3BzcihzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCkKPiAg ewo+ICAJdW5zaWduZWQgY2hhciBwc3JfZW47Cj4gKwlpbnQgcmV0Owo+IAo+ICAJLyogRGlzYWJs ZSBwc3IgZnVuY3Rpb24gKi8KPiAtCWRybV9kcF9kcGNkX3JlYWRiKCZkcC0+YXV4LCBEUF9QU1Jf RU5fQ0ZHLCAmcHNyX2VuKTsKPiArCXJldCA9IGRybV9kcF9kcGNkX3JlYWRiKCZkcC0+YXV4LCBE UF9QU1JfRU5fQ0ZHLCAmcHNyX2VuKTsKPiArCWlmIChyZXQgIT0gMSkgewo+ICsJCWRldl9lcnIo ZHAtPmRldiwgImZhaWxlZCB0byBnZXQgcHNyIGNvbmZpZ1xuIik7Cj4gKwkJZ290byBlbmQ7Cj4g Kwl9Cj4gKwo+ICAJcHNyX2VuICY9IH5EUF9QU1JfRU5BQkxFOwo+IC0JZHJtX2RwX2RwY2Rfd3Jp dGViKCZkcC0+YXV4LCBEUF9QU1JfRU5fQ0ZHLCBwc3JfZW4pOwo+ICsJcmV0ID0gZHJtX2RwX2Rw Y2Rfd3JpdGViKCZkcC0+YXV4LCBEUF9QU1JfRU5fQ0ZHLCBwc3JfZW4pOwo+ICsJaWYgKHJldCAh PSAxKSB7Cj4gKwkJZGV2X2VycihkcC0+ZGV2LCAiZmFpbGVkIHRvIGRpc2FibGUgcGFuZWwgcHNy XG4iKTsKPiArCQlnb3RvIGVuZDsKPiArCX0KPiAKPiAgCS8qIE1haW4tTGluayB0cmFuc21pdHRl ciByZW1haW5zIGFjdGl2ZSBkdXJpbmcgUFNSIGFjdGl2ZSBzdGF0ZXMgKi8KPiAgCXBzcl9lbiA9 IERQX1BTUl9NQUlOX0xJTktfQUNUSVZFIHwgRFBfUFNSX0NSQ19WRVJJRklDQVRJT047Cj4gLQlk cm1fZHBfZHBjZF93cml0ZWIoJmRwLT5hdXgsIERQX1BTUl9FTl9DRkcsIHBzcl9lbik7Cj4gKwly ZXQgPSBkcm1fZHBfZHBjZF93cml0ZWIoJmRwLT5hdXgsIERQX1BTUl9FTl9DRkcsIHBzcl9lbik7 Cj4gKwlpZiAocmV0ICE9IDEpIHsKPiArCQlkZXZfZXJyKGRwLT5kZXYsICJmYWlsZWQgdG8gc2V0 IHBhbmVsIHBzclxuIik7Cj4gKwkJZ290byBlbmQ7Cj4gKwl9Cj4gCj4gIAkvKiBFbmFibGUgcHNy IGZ1bmN0aW9uICovCj4gIAlwc3JfZW4gPSBEUF9QU1JfRU5BQkxFIHwgRFBfUFNSX01BSU5fTElO S19BQ1RJVkUgfAo+ICAJCSBEUF9QU1JfQ1JDX1ZFUklGSUNBVElPTjsKPiAtCWRybV9kcF9kcGNk X3dyaXRlYigmZHAtPmF1eCwgRFBfUFNSX0VOX0NGRywgcHNyX2VuKTsKPiArCXJldCA9IGRybV9k cF9kcGNkX3dyaXRlYigmZHAtPmF1eCwgRFBfUFNSX0VOX0NGRywgcHNyX2VuKTsKPiArCWlmIChy ZXQgIT0gMSkgewo+ICsJCWRldl9lcnIoZHAtPmRldiwgImZhaWxlZCB0byBzZXQgcGFuZWwgcHNy XG4iKTsKPiArCQlnb3RvIGVuZDsKPiArCX0KPiAKPiAgCWFuYWxvZ2l4X2RwX2VuYWJsZV9wc3Jf Y3JjKGRwKTsKPiArCj4gKwlyZXR1cm4gMDsKPiArZW5kOgo+ICsJZGV2X2VycihkcC0+ZGV2LCAi ZW5hYmxlIHBzciBmYWlsLCBmb3JjZSB0byBkaXNhYmxlIHBzclxuIik7Cj4gKwlkcC0+cHNyX2Vu YWJsZSA9IGZhbHNlOwo+ICsKPiArCXJldHVybiByZXQ7Cj4gIH0KPiAKPiAtc3RhdGljIHZvaWQK PiArc3RhdGljIGludAo+ICBhbmFsb2dpeF9kcF9lbmFibGVfcnhfdG9fZW5oYW5jZWRfbW9kZShz dHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCwKPiAgCQkJCSAgICAgICBib29sIGVuYWJsZSkK PiAgewo+ICAJdTggZGF0YTsKPiArCWludCByZXQ7Cj4gCj4gLQlkcm1fZHBfZHBjZF9yZWFkYigm ZHAtPmF1eCwgRFBfTEFORV9DT1VOVF9TRVQsICZkYXRhKTsKPiArCXJldCA9IGRybV9kcF9kcGNk X3JlYWRiKCZkcC0+YXV4LCBEUF9MQU5FX0NPVU5UX1NFVCwgJmRhdGEpOwo+ICsJaWYgKHJldCAh PSAxKQo+ICsJCXJldHVybiByZXQ7Cj4gCj4gIAlpZiAoZW5hYmxlKQo+IC0JCWRybV9kcF9kcGNk X3dyaXRlYigmZHAtPmF1eCwgRFBfTEFORV9DT1VOVF9TRVQsCj4gLQkJCQkgICBEUF9MQU5FX0NP VU5UX0VOSEFOQ0VEX0ZSQU1FX0VOIHwKPiAtCQkJCQlEUENEX0xBTkVfQ09VTlRfU0VUKGRhdGEp KTsKPiArCQlyZXQgPSBkcm1fZHBfZHBjZF93cml0ZWIoJmRwLT5hdXgsIERQX0xBTkVfQ09VTlRf U0VULAo+ICsJCQkJCSBEUF9MQU5FX0NPVU5UX0VOSEFOQ0VEX0ZSQU1FX0VOIHwKPiArCQkJCQkg RFBDRF9MQU5FX0NPVU5UX1NFVChkYXRhKSk7Cj4gIAllbHNlCj4gLQkJZHJtX2RwX2RwY2Rfd3Jp dGViKCZkcC0+YXV4LCBEUF9MQU5FX0NPVU5UX1NFVCwKPiAtCQkJCSAgIERQQ0RfTEFORV9DT1VO VF9TRVQoZGF0YSkpOwo+ICsJCXJldCA9IGRybV9kcF9kcGNkX3dyaXRlYigmZHAtPmF1eCwgRFBf TEFORV9DT1VOVF9TRVQsCj4gKwkJCQkJIERQQ0RfTEFORV9DT1VOVF9TRVQoZGF0YSkpOwo+ICsK PiArCXJldHVybiByZXQgPCAwID8gcmV0IDogMDsKPiAgfQo+IAo+IC1zdGF0aWMgaW50IGFuYWxv Z2l4X2RwX2lzX2VuaGFuY2VkX21vZGVfYXZhaWxhYmxlKHN0cnVjdAo+IGFuYWxvZ2l4X2RwX2Rl dmljZSAqZHApCj4gK3N0YXRpYyBpbnQgYW5hbG9naXhfZHBfaXNfZW5oYW5jZWRfbW9kZV9hdmFp bGFibGUoc3RydWN0Cj4gYW5hbG9naXhfZHBfZGV2aWNlICpkcCwKPiArCQkJCQkJICB1OCAqZW5o YW5jZWRfbW9kZV9zdXBwb3J0KQo+ICB7Cj4gIAl1OCBkYXRhOwo+IC0JaW50IHJldHZhbDsKPiAr CWludCByZXQ7Cj4gCj4gLQlkcm1fZHBfZHBjZF9yZWFkYigmZHAtPmF1eCwgRFBfTUFYX0xBTkVf Q09VTlQsICZkYXRhKTsKPiAtCXJldHZhbCA9IERQQ0RfRU5IQU5DRURfRlJBTUVfQ0FQKGRhdGEp Owo+ICsJcmV0ID0gZHJtX2RwX2RwY2RfcmVhZGIoJmRwLT5hdXgsIERQX01BWF9MQU5FX0NPVU5U LCAmZGF0YSk7Cj4gKwlpZiAocmV0ICE9IDEpIHsKPiArCQkqZW5oYW5jZWRfbW9kZV9zdXBwb3J0 ID0gMDsKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+IAo+IC0JcmV0dXJuIHJldHZhbDsKPiArCSpl bmhhbmNlZF9tb2RlX3N1cHBvcnQgPSBEUENEX0VOSEFOQ0VEX0ZSQU1FX0NBUChkYXRhKTsKPiAr Cj4gKwlyZXR1cm4gMDsKPiAgfQo+IAo+IC1zdGF0aWMgdm9pZCBhbmFsb2dpeF9kcF9zZXRfZW5o YW5jZWRfbW9kZShzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCkKPiArc3RhdGljIGludCBh bmFsb2dpeF9kcF9zZXRfZW5oYW5jZWRfbW9kZShzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpk cCkKPiAgewo+ICAJdTggZGF0YTsKPiArCWludCByZXQ7Cj4gKwo+ICsJcmV0ID0gYW5hbG9naXhf ZHBfaXNfZW5oYW5jZWRfbW9kZV9hdmFpbGFibGUoZHAsICZkYXRhKTsKPiArCWlmIChyZXQgPCAw KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJcmV0ID0gYW5hbG9naXhfZHBfZW5hYmxlX3J4X3Rv X2VuaGFuY2VkX21vZGUoZHAsIGRhdGEpOwo+ICsJaWYgKHJldCA8IDApCj4gKwkJcmV0dXJuIHJl dDsKPiAKPiAtCWRhdGEgPSBhbmFsb2dpeF9kcF9pc19lbmhhbmNlZF9tb2RlX2F2YWlsYWJsZShk cCk7Cj4gLQlhbmFsb2dpeF9kcF9lbmFibGVfcnhfdG9fZW5oYW5jZWRfbW9kZShkcCwgZGF0YSk7 Cj4gIAlhbmFsb2dpeF9kcF9lbmFibGVfZW5oYW5jZWRfbW9kZShkcCwgZGF0YSk7Cj4gKwo+ICsJ cmV0dXJuIDA7Cj4gIH0KPiAKPiAtc3RhdGljIHZvaWQgYW5hbG9naXhfZHBfdHJhaW5pbmdfcGF0 dGVybl9kaXMoc3RydWN0IGFuYWxvZ2l4X2RwX2RldmljZQo+ICpkcCkKPiArc3RhdGljIGludCBh bmFsb2dpeF9kcF90cmFpbmluZ19wYXR0ZXJuX2RpcyhzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNl CipkcCkKPiAgewo+ICsJaW50IHJldDsKPiArCj4gIAlhbmFsb2dpeF9kcF9zZXRfdHJhaW5pbmdf cGF0dGVybihkcCwgRFBfTk9ORSk7Cj4gCj4gLQlkcm1fZHBfZHBjZF93cml0ZWIoJmRwLT5hdXgs IERQX1RSQUlOSU5HX1BBVFRFUk5fU0VULAo+IC0JCQkgICBEUF9UUkFJTklOR19QQVRURVJOX0RJ U0FCTEUpOwo+ICsJcmV0ID0gZHJtX2RwX2RwY2Rfd3JpdGViKCZkcC0+YXV4LCBEUF9UUkFJTklO R19QQVRURVJOX1NFVCwKPiArCQkJCSBEUF9UUkFJTklOR19QQVRURVJOX0RJU0FCTEUpOwo+ICsK PiArCXJldHVybiByZXQgPCAwID8gcmV0IDogMDsKPiAgfQo+IAo+ICBzdGF0aWMgdm9pZAo+IEBA IC0yODIsNyArMzM5LDExIEBAIHN0YXRpYyBpbnQgYW5hbG9naXhfZHBfbGlua19zdGFydChzdHJ1 Y3QKPiBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+ICAJaWYgKHJldHZhbCA8IDApCj4gIAkJcmV0 dXJuIHJldHZhbDsKPiAgCS8qIHNldCBlbmhhbmNlZCBtb2RlIGlmIGF2YWlsYWJsZSAqLwo+IC0J YW5hbG9naXhfZHBfc2V0X2VuaGFuY2VkX21vZGUoZHApOwo+ICsJcmV0dmFsID0gYW5hbG9naXhf ZHBfc2V0X2VuaGFuY2VkX21vZGUoZHApOwo+ICsJaWYgKHJldHZhbCA8IDApIHsKPiArCQlkZXZf ZXJyKGRwLT5kZXYsICJmYWlsZWQgdG8gc2V0IGVuaGFuY2UgbW9kZVxuIik7Cj4gKwkJcmV0dXJu IHJldHZhbDsKPiArCX0KPiAKPiAgCS8qIFNldCBUWCBwcmUtZW1waGFzaXMgdG8gbWluaW11bSAq Lwo+ICAJZm9yIChsYW5lID0gMDsgbGFuZSA8IGxhbmVfY291bnQ7IGxhbmUrKykKPiBAQCAtNTY3 LDEwICs2MjgsMTEgQEAgc3RhdGljIGludAo+IGFuYWxvZ2l4X2RwX3Byb2Nlc3NfZXF1YWxpemVy X3RyYWluaW5nKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+IAo+ICAJaWYgKCFhbmFs b2dpeF9kcF9jaGFubmVsX2VxX29rKGxpbmtfc3RhdHVzLCBsaW5rX2FsaWduLCBsYW5lX2NvdW50 KSkKPiB7Cj4gIAkJLyogdHJhaW5nIHBhdHRlcm4gU2V0IHRvIE5vcm1hbCAqLwo+IC0JCWFuYWxv Z2l4X2RwX3RyYWluaW5nX3BhdHRlcm5fZGlzKGRwKTsKPiArCQlyZXR2YWwgPSBhbmFsb2dpeF9k cF90cmFpbmluZ19wYXR0ZXJuX2RpcyhkcCk7Cj4gKwkJaWYgKHJldHZhbCA8IDApCj4gKwkJCXJl dHVybiByZXR2YWw7Cj4gCj4gIAkJZGV2X2luZm8oZHAtPmRldiwgIkxpbmsgVHJhaW5pbmcgc3Vj Y2VzcyFcbiIpOwo+IC0KPiAgCQlhbmFsb2dpeF9kcF9nZXRfbGlua19iYW5kd2lkdGgoZHAsICZy ZWcpOwo+ICAJCWRwLT5saW5rX3RyYWluLmxpbmtfcmF0ZSA9IHJlZzsKPiAgCQlkZXZfZGJnKGRw LT5kZXYsICJmaW5hbCBiYW5kd2lkdGggPSAlLjJ4XG4iLAo+IEBAIC04NjcsMjQgKzkyOSwzMiBA QCBzdGF0aWMgaW50IGFuYWxvZ2l4X2RwX2NvbmZpZ192aWRlbyhzdHJ1Y3QKPiBhbmFsb2dpeF9k cF9kZXZpY2UgKmRwKQo+ICAJcmV0dXJuIDA7Cj4gIH0KPiAKPiAtc3RhdGljIHZvaWQgYW5hbG9n aXhfZHBfZW5hYmxlX3NjcmFtYmxlKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwLAo+IC0J CQkJCWJvb2wgZW5hYmxlKQo+ICtzdGF0aWMgaW50IGFuYWxvZ2l4X2RwX2VuYWJsZV9zY3JhbWJs ZShzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCwKPiArCQkJCSAgICAgICBib29sIGVuYWJs ZSkKPiAgewo+ICAJdTggZGF0YTsKPiArCWludCByZXQ7Cj4gCj4gIAlpZiAoZW5hYmxlKSB7Cj4g IAkJYW5hbG9naXhfZHBfZW5hYmxlX3NjcmFtYmxpbmcoZHApOwo+IAo+IC0JCWRybV9kcF9kcGNk X3JlYWRiKCZkcC0+YXV4LCBEUF9UUkFJTklOR19QQVRURVJOX1NFVCwgJmRhdGEpOwo+IC0JCWRy bV9kcF9kcGNkX3dyaXRlYigmZHAtPmF1eCwgRFBfVFJBSU5JTkdfUEFUVEVSTl9TRVQsCj4gKwkJ cmV0ID0gZHJtX2RwX2RwY2RfcmVhZGIoJmRwLT5hdXgsIERQX1RSQUlOSU5HX1BBVFRFUk5fU0VU LAo+ICsJCQkJCSZkYXRhKTsKPiArCQlpZiAocmV0ICE9IDEpCj4gKwkJCXJldHVybiByZXQ7Cj4g KwkJcmV0ID0gZHJtX2RwX2RwY2Rfd3JpdGViKCZkcC0+YXV4LCBEUF9UUkFJTklOR19QQVRURVJO X1NFVCwKPiAgCQkJCSAgICh1OCkoZGF0YSAmCn5EUF9MSU5LX1NDUkFNQkxJTkdfRElTQUJMRSkp Owo+ICAJfSBlbHNlIHsKPiAgCQlhbmFsb2dpeF9kcF9kaXNhYmxlX3NjcmFtYmxpbmcoZHApOwo+ IAo+IC0JCWRybV9kcF9kcGNkX3JlYWRiKCZkcC0+YXV4LCBEUF9UUkFJTklOR19QQVRURVJOX1NF VCwgJmRhdGEpOwo+IC0JCWRybV9kcF9kcGNkX3dyaXRlYigmZHAtPmF1eCwgRFBfVFJBSU5JTkdf UEFUVEVSTl9TRVQsCj4gKwkJcmV0ID0gZHJtX2RwX2RwY2RfcmVhZGIoJmRwLT5hdXgsIERQX1RS QUlOSU5HX1BBVFRFUk5fU0VULAo+ICsJCQkJCSZkYXRhKTsKPiArCQlpZiAocmV0ICE9IDEpCj4g KwkJCXJldHVybiByZXQ7Cj4gKwkJcmV0ID0gZHJtX2RwX2RwY2Rfd3JpdGViKCZkcC0+YXV4LCBE UF9UUkFJTklOR19QQVRURVJOX1NFVCwKPiAgCQkJCSAgICh1OCkoZGF0YSB8IERQX0xJTktfU0NS QU1CTElOR19ESVNBQkxFKSk7Cj4gIAl9Cj4gKwlyZXR1cm4gcmV0IDwgMCA/IHJldCA6IDA7Cj4g IH0KPiAKPiAgc3RhdGljIGlycXJldHVybl90IGFuYWxvZ2l4X2RwX2hhcmRpcnEoaW50IGlycSwg dm9pZCAqYXJnKQo+IEBAIC05MzksMjMgKzEwMDksMzYgQEAgc3RhdGljIGludCBhbmFsb2dpeF9k cF9jb21taXQoc3RydWN0Cj4gYW5hbG9naXhfZHBfZGV2aWNlICpkcCkKPiAgCQlyZXR1cm4gcmV0 Owo+ICAJfQo+IAo+IC0JYW5hbG9naXhfZHBfZW5hYmxlX3NjcmFtYmxlKGRwLCAxKTsKPiArCXJl dCA9IGFuYWxvZ2l4X2RwX2VuYWJsZV9zY3JhbWJsZShkcCwgMSk7Cj4gKwlpZiAocmV0IDwgMCkg ewo+ICsJCWRldl9lcnIoZHAtPmRldiwgImNhbiBub3QgZW5hYmxlIHNjcmFtYmxlXG4iKTsKPiAr CQlyZXR1cm4gcmV0Owo+ICsJfQo+IAo+ICAJYW5hbG9naXhfZHBfaW5pdF92aWRlbyhkcCk7Cj4g IAlyZXQgPSBhbmFsb2dpeF9kcF9jb25maWdfdmlkZW8oZHApOwo+IC0JaWYgKHJldCkKPiArCWlm IChyZXQpIHsKPiAgCQlkZXZfZXJyKGRwLT5kZXYsICJ1bmFibGUgdG8gY29uZmlnIHZpZGVvXG4i KTsKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+IAo+ICAJLyogU2FmZSB0byBlbmFibGUgdGhlIHBh bmVsIG5vdyAqLwo+ICAJaWYgKGRwLT5wbGF0X2RhdGEtPnBhbmVsKSB7Cj4gLQkJaWYgKGRybV9w YW5lbF9lbmFibGUoZHAtPnBsYXRfZGF0YS0+cGFuZWwpKQo+ICsJCXJldCA9IGRybV9wYW5lbF9l bmFibGUoZHAtPnBsYXRfZGF0YS0+cGFuZWwpOwo+ICsJCWlmIChyZXQpIHsKPiAgCQkJRFJNX0VS Uk9SKCJmYWlsZWQgdG8gZW5hYmxlIHRoZSBwYW5lbFxuIik7Cj4gKwkJCXJldHVybiByZXQ7Cj4g KwkJfQo+ICAJfQo+IAo+IC0JZHAtPnBzcl9lbmFibGUgPSBhbmFsb2dpeF9kcF9kZXRlY3Rfc2lu a19wc3IoZHApOwo+ICsJcmV0ID0gYW5hbG9naXhfZHBfZGV0ZWN0X3NpbmtfcHNyKGRwKTsKPiAr CWlmIChyZXQpCj4gKwkJcmV0dXJuIHJldDsKPiArCj4gIAlpZiAoZHAtPnBzcl9lbmFibGUpCj4g LQkJYW5hbG9naXhfZHBfZW5hYmxlX3NpbmtfcHNyKGRwKTsKPiAtCXJldHVybiAwOwo+ICsJCXJl dCA9IGFuYWxvZ2l4X2RwX2VuYWJsZV9zaW5rX3BzcihkcCk7Cj4gKwo+ICsJcmV0dXJuIHJldDsK PiAgfQo+IAo+ICAvKgo+IEBAIC0xMTg1LDggKzEyNjgsMTAgQEAgc3RhdGljIGludCBhbmFsb2dp eF9kcF9zZXRfYnJpZGdlKHN0cnVjdAo+IGFuYWxvZ2l4X2RwX2RldmljZSAqZHApCj4gIAl9Cj4g Cj4gIAlyZXQgPSBhbmFsb2dpeF9kcF9jb21taXQoZHApOwo+IC0JaWYgKHJldCkKPiArCWlmIChy ZXQpIHsKPiArCQlEUk1fRVJST1IoImRwIGNvbW1pdCBlcnJvciwgcmV0ID0gJWRcbiIsIHJldCk7 Cj4gIAkJZ290byBvdXRfZHBfaW5pdDsKPiArCX0KPiAKPiAgCWVuYWJsZV9pcnEoZHAtPmlycSk7 Cj4gIAlyZXR1cm4gMDsKPiAtLQo+IDIuMTcuMAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxp c3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFu L2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: jingoohan1@gmail.com (Jingoo Han) Date: Tue, 24 Apr 2018 09:54:04 -0400 Subject: [RESEND PATCH v6 10/27] drm/bridge: analogix_dp: Check dpcd write/read status In-Reply-To: <20180423105003.9004-11-enric.balletbo@collabora.com> References: <20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-11-enric.balletbo@collabora.com> Message-ID: <000201d3dbd3$b70de580$2529b080$@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Monday, April 23, 2018 6:50 AM, Enric Balletbo i Serra wrote: > > From: Lin Huang > > We need to check the dpcd write/read return value to see whether the > write/read was successful > > Cc: Kristian H. Kristensen > Signed-off-by: Lin Huang > Signed-off-by: zain wang > Signed-off-by: Douglas Anderson > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Reviewed-by: Andrzej Hajda > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > Reviewed-by: Archit Taneja Acked-by: Jingoo Han Best regards, Jingoo Han > --- > > .../drm/bridge/analogix/analogix_dp_core.c | 169 +++++++++++++----- > 1 file changed, 127 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > index 1e1743b59c77..75e61ebf6722 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > @@ -160,80 +160,137 @@ int analogix_dp_disable_psr(struct > analogix_dp_device *dp) > } > EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); > > -static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) > +static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) > { > unsigned char psr_version; > + int ret; > + > + ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); > + if (ret != 1) { > + dev_err(dp->dev, "failed to get PSR version, disable it\n"); > + return ret; > + } > > - drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); > dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); > > - return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; > + dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; > + > + return 0; > } > > -static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) > +static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) > { > unsigned char psr_en; > + int ret; > > /* Disable psr function */ > - drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en); > + ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en); > + if (ret != 1) { > + dev_err(dp->dev, "failed to get psr config\n"); > + goto end; > + } > + > psr_en &= ~DP_PSR_ENABLE; > - drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + if (ret != 1) { > + dev_err(dp->dev, "failed to disable panel psr\n"); > + goto end; > + } > > /* Main-Link transmitter remains active during PSR active states */ > psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; > - drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + if (ret != 1) { > + dev_err(dp->dev, "failed to set panel psr\n"); > + goto end; > + } > > /* Enable psr function */ > psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | > DP_PSR_CRC_VERIFICATION; > - drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + if (ret != 1) { > + dev_err(dp->dev, "failed to set panel psr\n"); > + goto end; > + } > > analogix_dp_enable_psr_crc(dp); > + > + return 0; > +end: > + dev_err(dp->dev, "enable psr fail, force to disable psr\n"); > + dp->psr_enable = false; > + > + return ret; > } > > -static void > +static int > analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, > bool enable) > { > u8 data; > + int ret; > > - drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); > + ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); > + if (ret != 1) > + return ret; > > if (enable) > - drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, > - DP_LANE_COUNT_ENHANCED_FRAME_EN | > - DPCD_LANE_COUNT_SET(data)); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, > + DP_LANE_COUNT_ENHANCED_FRAME_EN | > + DPCD_LANE_COUNT_SET(data)); > else > - drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, > - DPCD_LANE_COUNT_SET(data)); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, > + DPCD_LANE_COUNT_SET(data)); > + > + return ret < 0 ? ret : 0; > } > > -static int analogix_dp_is_enhanced_mode_available(struct > analogix_dp_device *dp) > +static int analogix_dp_is_enhanced_mode_available(struct > analogix_dp_device *dp, > + u8 *enhanced_mode_support) > { > u8 data; > - int retval; > + int ret; > > - drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); > - retval = DPCD_ENHANCED_FRAME_CAP(data); > + ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); > + if (ret != 1) { > + *enhanced_mode_support = 0; > + return ret; > + } > > - return retval; > + *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data); > + > + return 0; > } > > -static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) > +static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) > { > u8 data; > + int ret; > + > + ret = analogix_dp_is_enhanced_mode_available(dp, &data); > + if (ret < 0) > + return ret; > + > + ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data); > + if (ret < 0) > + return ret; > > - data = analogix_dp_is_enhanced_mode_available(dp); > - analogix_dp_enable_rx_to_enhanced_mode(dp, data); > analogix_dp_enable_enhanced_mode(dp, data); > + > + return 0; > } > > -static void analogix_dp_training_pattern_dis(struct analogix_dp_device > *dp) > +static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) > { > + int ret; > + > analogix_dp_set_training_pattern(dp, DP_NONE); > > - drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > - DP_TRAINING_PATTERN_DISABLE); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > + DP_TRAINING_PATTERN_DISABLE); > + > + return ret < 0 ? ret : 0; > } > > static void > @@ -282,7 +339,11 @@ static int analogix_dp_link_start(struct > analogix_dp_device *dp) > if (retval < 0) > return retval; > /* set enhanced mode if available */ > - analogix_dp_set_enhanced_mode(dp); > + retval = analogix_dp_set_enhanced_mode(dp); > + if (retval < 0) { > + dev_err(dp->dev, "failed to set enhance mode\n"); > + return retval; > + } > > /* Set TX pre-emphasis to minimum */ > for (lane = 0; lane < lane_count; lane++) > @@ -567,10 +628,11 @@ static int > analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) > > if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) > { > /* traing pattern Set to Normal */ > - analogix_dp_training_pattern_dis(dp); > + retval = analogix_dp_training_pattern_dis(dp); > + if (retval < 0) > + return retval; > > dev_info(dp->dev, "Link Training success!\n"); > - > analogix_dp_get_link_bandwidth(dp, ®); > dp->link_train.link_rate = reg; > dev_dbg(dp->dev, "final bandwidth = %.2x\n", > @@ -867,24 +929,32 @@ static int analogix_dp_config_video(struct > analogix_dp_device *dp) > return 0; > } > > -static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, > - bool enable) > +static int analogix_dp_enable_scramble(struct analogix_dp_device *dp, > + bool enable) > { > u8 data; > + int ret; > > if (enable) { > analogix_dp_enable_scrambling(dp); > > - drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); > - drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > + ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, > + &data); > + if (ret != 1) > + return ret; > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); > } else { > analogix_dp_disable_scrambling(dp); > > - drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); > - drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > + ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, > + &data); > + if (ret != 1) > + return ret; > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); > } > + return ret < 0 ? ret : 0; > } > > static irqreturn_t analogix_dp_hardirq(int irq, void *arg) > @@ -939,23 +1009,36 @@ static int analogix_dp_commit(struct > analogix_dp_device *dp) > return ret; > } > > - analogix_dp_enable_scramble(dp, 1); > + ret = analogix_dp_enable_scramble(dp, 1); > + if (ret < 0) { > + dev_err(dp->dev, "can not enable scramble\n"); > + return ret; > + } > > analogix_dp_init_video(dp); > ret = analogix_dp_config_video(dp); > - if (ret) > + if (ret) { > dev_err(dp->dev, "unable to config video\n"); > + return ret; > + } > > /* Safe to enable the panel now */ > if (dp->plat_data->panel) { > - if (drm_panel_enable(dp->plat_data->panel)) > + ret = drm_panel_enable(dp->plat_data->panel); > + if (ret) { > DRM_ERROR("failed to enable the panel\n"); > + return ret; > + } > } > > - dp->psr_enable = analogix_dp_detect_sink_psr(dp); > + ret = analogix_dp_detect_sink_psr(dp); > + if (ret) > + return ret; > + > if (dp->psr_enable) > - analogix_dp_enable_sink_psr(dp); > - return 0; > + ret = analogix_dp_enable_sink_psr(dp); > + > + return ret; > } > > /* > @@ -1185,8 +1268,10 @@ static int analogix_dp_set_bridge(struct > analogix_dp_device *dp) > } > > ret = analogix_dp_commit(dp); > - if (ret) > + if (ret) { > + DRM_ERROR("dp commit error, ret = %d\n", ret); > goto out_dp_init; > + } > > enable_irq(dp->irq); > return 0; > -- > 2.17.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758211AbeDXNyS (ORCPT ); Tue, 24 Apr 2018 09:54:18 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:38481 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758129AbeDXNyJ (ORCPT ); Tue, 24 Apr 2018 09:54:09 -0400 X-Google-Smtp-Source: AB8JxZoqbfAcf2X8IoBKQfdhnRfbh+hTN1bleYZ1C2P2G/kqmFowvpoRo+Bk4L9ZaWrQCbla8OxaYQ== From: "Jingoo Han" To: "'Enric Balletbo i Serra'" , , , , , , , , Cc: , , , , , , , , , , , , , , , , , , , , , , , "'Kristian H . Kristensen'" References: <20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-11-enric.balletbo@collabora.com> In-Reply-To: <20180423105003.9004-11-enric.balletbo@collabora.com> Subject: Re: [RESEND PATCH v6 10/27] drm/bridge: analogix_dp: Check dpcd write/read status Date: Tue, 24 Apr 2018 09:54:04 -0400 Message-ID: <000201d3dbd3$b70de580$2529b080$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQJsKqzGdLQ3B8H319FIYPcigFOt/AFKGD0jotUBCbA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday, April 23, 2018 6:50 AM, Enric Balletbo i Serra wrote: > > From: Lin Huang > > We need to check the dpcd write/read return value to see whether the > write/read was successful > > Cc: Kristian H. Kristensen > Signed-off-by: Lin Huang > Signed-off-by: zain wang > Signed-off-by: Douglas Anderson > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Reviewed-by: Andrzej Hajda > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > Reviewed-by: Archit Taneja Acked-by: Jingoo Han Best regards, Jingoo Han > --- > > .../drm/bridge/analogix/analogix_dp_core.c | 169 +++++++++++++----- > 1 file changed, 127 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > index 1e1743b59c77..75e61ebf6722 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > @@ -160,80 +160,137 @@ int analogix_dp_disable_psr(struct > analogix_dp_device *dp) > } > EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); > > -static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) > +static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) > { > unsigned char psr_version; > + int ret; > + > + ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); > + if (ret != 1) { > + dev_err(dp->dev, "failed to get PSR version, disable it\n"); > + return ret; > + } > > - drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); > dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); > > - return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; > + dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; > + > + return 0; > } > > -static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) > +static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) > { > unsigned char psr_en; > + int ret; > > /* Disable psr function */ > - drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en); > + ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en); > + if (ret != 1) { > + dev_err(dp->dev, "failed to get psr config\n"); > + goto end; > + } > + > psr_en &= ~DP_PSR_ENABLE; > - drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + if (ret != 1) { > + dev_err(dp->dev, "failed to disable panel psr\n"); > + goto end; > + } > > /* Main-Link transmitter remains active during PSR active states */ > psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; > - drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + if (ret != 1) { > + dev_err(dp->dev, "failed to set panel psr\n"); > + goto end; > + } > > /* Enable psr function */ > psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | > DP_PSR_CRC_VERIFICATION; > - drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); > + if (ret != 1) { > + dev_err(dp->dev, "failed to set panel psr\n"); > + goto end; > + } > > analogix_dp_enable_psr_crc(dp); > + > + return 0; > +end: > + dev_err(dp->dev, "enable psr fail, force to disable psr\n"); > + dp->psr_enable = false; > + > + return ret; > } > > -static void > +static int > analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, > bool enable) > { > u8 data; > + int ret; > > - drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); > + ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); > + if (ret != 1) > + return ret; > > if (enable) > - drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, > - DP_LANE_COUNT_ENHANCED_FRAME_EN | > - DPCD_LANE_COUNT_SET(data)); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, > + DP_LANE_COUNT_ENHANCED_FRAME_EN | > + DPCD_LANE_COUNT_SET(data)); > else > - drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, > - DPCD_LANE_COUNT_SET(data)); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, > + DPCD_LANE_COUNT_SET(data)); > + > + return ret < 0 ? ret : 0; > } > > -static int analogix_dp_is_enhanced_mode_available(struct > analogix_dp_device *dp) > +static int analogix_dp_is_enhanced_mode_available(struct > analogix_dp_device *dp, > + u8 *enhanced_mode_support) > { > u8 data; > - int retval; > + int ret; > > - drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); > - retval = DPCD_ENHANCED_FRAME_CAP(data); > + ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); > + if (ret != 1) { > + *enhanced_mode_support = 0; > + return ret; > + } > > - return retval; > + *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data); > + > + return 0; > } > > -static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) > +static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) > { > u8 data; > + int ret; > + > + ret = analogix_dp_is_enhanced_mode_available(dp, &data); > + if (ret < 0) > + return ret; > + > + ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data); > + if (ret < 0) > + return ret; > > - data = analogix_dp_is_enhanced_mode_available(dp); > - analogix_dp_enable_rx_to_enhanced_mode(dp, data); > analogix_dp_enable_enhanced_mode(dp, data); > + > + return 0; > } > > -static void analogix_dp_training_pattern_dis(struct analogix_dp_device > *dp) > +static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) > { > + int ret; > + > analogix_dp_set_training_pattern(dp, DP_NONE); > > - drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > - DP_TRAINING_PATTERN_DISABLE); > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > + DP_TRAINING_PATTERN_DISABLE); > + > + return ret < 0 ? ret : 0; > } > > static void > @@ -282,7 +339,11 @@ static int analogix_dp_link_start(struct > analogix_dp_device *dp) > if (retval < 0) > return retval; > /* set enhanced mode if available */ > - analogix_dp_set_enhanced_mode(dp); > + retval = analogix_dp_set_enhanced_mode(dp); > + if (retval < 0) { > + dev_err(dp->dev, "failed to set enhance mode\n"); > + return retval; > + } > > /* Set TX pre-emphasis to minimum */ > for (lane = 0; lane < lane_count; lane++) > @@ -567,10 +628,11 @@ static int > analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) > > if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) > { > /* traing pattern Set to Normal */ > - analogix_dp_training_pattern_dis(dp); > + retval = analogix_dp_training_pattern_dis(dp); > + if (retval < 0) > + return retval; > > dev_info(dp->dev, "Link Training success!\n"); > - > analogix_dp_get_link_bandwidth(dp, ®); > dp->link_train.link_rate = reg; > dev_dbg(dp->dev, "final bandwidth = %.2x\n", > @@ -867,24 +929,32 @@ static int analogix_dp_config_video(struct > analogix_dp_device *dp) > return 0; > } > > -static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, > - bool enable) > +static int analogix_dp_enable_scramble(struct analogix_dp_device *dp, > + bool enable) > { > u8 data; > + int ret; > > if (enable) { > analogix_dp_enable_scrambling(dp); > > - drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); > - drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > + ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, > + &data); > + if (ret != 1) > + return ret; > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); > } else { > analogix_dp_disable_scrambling(dp); > > - drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); > - drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > + ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, > + &data); > + if (ret != 1) > + return ret; > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, > (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); > } > + return ret < 0 ? ret : 0; > } > > static irqreturn_t analogix_dp_hardirq(int irq, void *arg) > @@ -939,23 +1009,36 @@ static int analogix_dp_commit(struct > analogix_dp_device *dp) > return ret; > } > > - analogix_dp_enable_scramble(dp, 1); > + ret = analogix_dp_enable_scramble(dp, 1); > + if (ret < 0) { > + dev_err(dp->dev, "can not enable scramble\n"); > + return ret; > + } > > analogix_dp_init_video(dp); > ret = analogix_dp_config_video(dp); > - if (ret) > + if (ret) { > dev_err(dp->dev, "unable to config video\n"); > + return ret; > + } > > /* Safe to enable the panel now */ > if (dp->plat_data->panel) { > - if (drm_panel_enable(dp->plat_data->panel)) > + ret = drm_panel_enable(dp->plat_data->panel); > + if (ret) { > DRM_ERROR("failed to enable the panel\n"); > + return ret; > + } > } > > - dp->psr_enable = analogix_dp_detect_sink_psr(dp); > + ret = analogix_dp_detect_sink_psr(dp); > + if (ret) > + return ret; > + > if (dp->psr_enable) > - analogix_dp_enable_sink_psr(dp); > - return 0; > + ret = analogix_dp_enable_sink_psr(dp); > + > + return ret; > } > > /* > @@ -1185,8 +1268,10 @@ static int analogix_dp_set_bridge(struct > analogix_dp_device *dp) > } > > ret = analogix_dp_commit(dp); > - if (ret) > + if (ret) { > + DRM_ERROR("dp commit error, ret = %d\n", ret); > goto out_dp_init; > + } > > enable_irq(dp->irq); > return 0; > -- > 2.17.0