From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jingoo Han" Subject: Re: [RESEND PATCH v6 11/27] drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip Date: Tue, 24 Apr 2018 09:57:01 -0400 Message-ID: <000301d3dbd4$20be52d0$623af870$@gmail.com> References: <20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-12-enric.balletbo@collabora.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180423105003.9004-12-enric.balletbo@collabora.com> Content-Language: en-us List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: 'Enric Balletbo i Serra' , architt@codeaurora.org, inki.dae@samsung.com, thierry.reding@gmail.com, hjc@rock-chips.com, seanpaul@chromium.org, airlied@linux.ie, tfiga@chromium.org, heiko@sntech.de Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Laurent.pinchart@ideasonboard.com, kernel@collabora.com, m.szyprowski@samsung.com, linux-samsung-soc@vger.kernel.org, rydberg@bitmath.org, krzk@kernel.org, linux-rockchip@lists.infradead.org, kgene@kernel.org, orjan.eide@arm.com, wxt@rock-chips.com, jeffy.chen@rock-chips.com, linux-arm-kernel@lists.infradead.org, wzz@rock-chips.com, hl@rock-chips.com, sw0312.kim@samsung.com, dianders@chromium.org, kyungmin.park@samsung.com, kuankuan.y@gmail.com, hshi@chromium.org List-Id: linux-rockchip.vger.kernel.org T24gTW9uZGF5LCBBcHJpbCAyMywgMjAxOCA2OjUwIEFNLCBFbnJpYyBCYWxsZXRibyBpIFNlcnJh IHdyb3RlOgo+IAo+IEZyb206IHphaW4gd2FuZyA8d3p6QHJvY2stY2hpcHMuY29tPgo+IAo+IFRo ZXJlIGFyZSBzb21lIGRpZmZlcmVudCBiaXRzIGJldHdlZW4gUm9ja2NoaXAgYW5kIEV4eW5vcyBp biByZWdpc3Rlcgo+ICJBVVhfUEQiLiBUaGlzIHBhdGNoIGZpeGVzIHRoZSBpbmNvcnJlY3Qgb3Bl cmF0aW9ucyBhYm91dCBpdC4KPiAKPiBDYzogRG91Z2xhcyBBbmRlcnNvbiA8ZGlhbmRlcnNAY2hy b21pdW0ub3JnPgo+IFNpZ25lZC1vZmYtYnk6IHphaW4gd2FuZyA8d3p6QHJvY2stY2hpcHMuY29t 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UEQJCQkJCSgweDEgPDwgMSkKPiAtLQo+IDIuMTcuMAoKCl9fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVs QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWls bWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: jingoohan1@gmail.com (Jingoo Han) Date: Tue, 24 Apr 2018 09:57:01 -0400 Subject: [RESEND PATCH v6 11/27] drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip In-Reply-To: <20180423105003.9004-12-enric.balletbo@collabora.com> References: <20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-12-enric.balletbo@collabora.com> Message-ID: <000301d3dbd4$20be52d0$623af870$@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Monday, April 23, 2018 6:50 AM, Enric Balletbo i Serra wrote: > > From: zain wang > > There are some different bits between Rockchip and Exynos in register > "AUX_PD". This patch fixes the incorrect operations about it. > > Cc: Douglas Anderson > Signed-off-by: zain wang > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Reviewed-by: Andrzej Hajda > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > Reviewed-by: Archit Taneja Acked-by: Jingoo Han Best regards, Jingoo Han > --- > > .../gpu/drm/bridge/analogix/analogix_dp_reg.c | 117 ++++++++++-------- > .../gpu/drm/bridge/analogix/analogix_dp_reg.h | 2 + > 2 files changed, 65 insertions(+), 54 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index bb72f8b0e603..dee1ba109b5f 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -248,76 +248,85 @@ void analogix_dp_set_analog_power_down(struct > analogix_dp_device *dp, > { > u32 reg; > u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; > + u32 mask; > > if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > phy_pd_addr = ANALOGIX_DP_PD; > > switch (block) { > case AUX_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= AUX_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~AUX_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + mask = RK_AUX_PD; > + else > + mask = AUX_PD; > + > + reg = readl(dp->reg_base + phy_pd_addr); > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH0_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH0_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH0_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH0_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH1_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH1_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH1_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH1_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH2_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH2_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH2_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH2_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH3_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH3_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH3_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH3_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case ANALOG_TOTAL: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= DP_PHY_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~DP_PHY_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + /* > + * There is no bit named DP_PHY_PD, so We used DP_INC_BG > + * to power off everything instead of DP_PHY_PD in > + * Rockchip > + */ > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + mask = DP_INC_BG; > + else > + mask = DP_PHY_PD; > + > + reg = readl(dp->reg_base + phy_pd_addr); > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + > + writel(reg, dp->reg_base + phy_pd_addr); > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + usleep_range(10, 15); > break; > case POWER_ALL: > if (enable) { > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > index 9602668669f4..b633a4a5082a 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > @@ -345,7 +345,9 @@ > #define DP_INC_BG (0x1 << 7) > #define DP_EXP_BG (0x1 << 6) > #define DP_PHY_PD (0x1 << 5) > +#define RK_AUX_PD (0x1 << 5) > #define AUX_PD (0x1 << 4) > +#define RK_PLL_PD (0x1 << 4) > #define CH3_PD (0x1 << 3) > #define CH2_PD (0x1 << 2) > #define CH1_PD (0x1 << 1) > -- > 2.17.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933537AbeDXN5Q (ORCPT ); Tue, 24 Apr 2018 09:57:16 -0400 Received: from mail-qt0-f195.google.com ([209.85.216.195]:41608 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758221AbeDXN5H (ORCPT ); Tue, 24 Apr 2018 09:57:07 -0400 X-Google-Smtp-Source: AB8JxZp+Es1e4K8oP1bveIdM2voR5lpjiMdeCnClOrwxUQ4JHRcH1ILAZASaj4OFKlCq+phCvTe1hA== From: "Jingoo Han" To: "'Enric Balletbo i Serra'" , , , , , , , , Cc: , , , , , , , , , , , , , , , , , , , , , , References: <20180423105003.9004-1-enric.balletbo@collabora.com> <20180423105003.9004-12-enric.balletbo@collabora.com> In-Reply-To: <20180423105003.9004-12-enric.balletbo@collabora.com> Subject: Re: [RESEND PATCH v6 11/27] drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip Date: Tue, 24 Apr 2018 09:57:01 -0400 Message-ID: <000301d3dbd4$20be52d0$623af870$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQJsKqzGdLQ3B8H319FIYPcigFOt/AJcUxiHosxwDZA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday, April 23, 2018 6:50 AM, Enric Balletbo i Serra wrote: > > From: zain wang > > There are some different bits between Rockchip and Exynos in register > "AUX_PD". This patch fixes the incorrect operations about it. > > Cc: Douglas Anderson > Signed-off-by: zain wang > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Reviewed-by: Andrzej Hajda > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > Reviewed-by: Archit Taneja Acked-by: Jingoo Han Best regards, Jingoo Han > --- > > .../gpu/drm/bridge/analogix/analogix_dp_reg.c | 117 ++++++++++-------- > .../gpu/drm/bridge/analogix/analogix_dp_reg.h | 2 + > 2 files changed, 65 insertions(+), 54 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index bb72f8b0e603..dee1ba109b5f 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -248,76 +248,85 @@ void analogix_dp_set_analog_power_down(struct > analogix_dp_device *dp, > { > u32 reg; > u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; > + u32 mask; > > if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > phy_pd_addr = ANALOGIX_DP_PD; > > switch (block) { > case AUX_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= AUX_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~AUX_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + mask = RK_AUX_PD; > + else > + mask = AUX_PD; > + > + reg = readl(dp->reg_base + phy_pd_addr); > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH0_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH0_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH0_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH0_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH1_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH1_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH1_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH1_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH2_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH2_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH2_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH2_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH3_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH3_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH3_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH3_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case ANALOG_TOTAL: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= DP_PHY_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~DP_PHY_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + /* > + * There is no bit named DP_PHY_PD, so We used DP_INC_BG > + * to power off everything instead of DP_PHY_PD in > + * Rockchip > + */ > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + mask = DP_INC_BG; > + else > + mask = DP_PHY_PD; > + > + reg = readl(dp->reg_base + phy_pd_addr); > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + > + writel(reg, dp->reg_base + phy_pd_addr); > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + usleep_range(10, 15); > break; > case POWER_ALL: > if (enable) { > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > index 9602668669f4..b633a4a5082a 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > @@ -345,7 +345,9 @@ > #define DP_INC_BG (0x1 << 7) > #define DP_EXP_BG (0x1 << 6) > #define DP_PHY_PD (0x1 << 5) > +#define RK_AUX_PD (0x1 << 5) > #define AUX_PD (0x1 << 4) > +#define RK_PLL_PD (0x1 << 4) > #define CH3_PD (0x1 << 3) > #define CH2_PD (0x1 << 2) > #define CH1_PD (0x1 << 1) > -- > 2.17.0