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diff for duplicates of <000401d37a7b$61e574b0$25b05e10$@gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index 9b904be..a6de458 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,16 +1,14 @@
 On Wednesday, December 20, 2017 2:33 PM, Joao Pinto wrote:
->=20
->=20
+> 
+> 
 > Hi,
->=20
-> =C3=80s 11:29 PM de 12/19/2017, Niklas Cassel escreveu:
+> 
+> Às 11:29 PM de 12/19/2017, Niklas Cassel escreveu:
 > > Add a generic function for raising MSI irqs that can be used by all
 > > DWC based controllers.
 > >
-> > Note that certain controllers, like DRA7xx, have a special =
-convenience
-> > register for raising MSI irqs that doesn't require you to explicitly =
-map
+> > Note that certain controllers, like DRA7xx, have a special convenience
+> > register for raising MSI irqs that doesn't require you to explicitly map
 > > the MSI address. Therefore, it is likely that certain drivers will
 > > not use this generic function, even if they can.
 > >
@@ -26,15 +24,15 @@ map
 > > index 700ed2f4becf..c5aa1cac5041 100644
 > > --- a/drivers/pci/dwc/pcie-designware-ep.c
 > > +++ b/drivers/pci/dwc/pcie-designware-ep.c
-> > @@ -282,6 +282,41 @@ static const struct pci_epc_ops epc_ops =3D {
-> >  	.stop			=3D dw_pcie_ep_stop,
+> > @@ -282,6 +282,41 @@ static const struct pci_epc_ops epc_ops = {
+> >  	.stop			= dw_pcie_ep_stop,
 > >  };
 > >
 > > +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
 > > +			     u8 interrupt_num)
 > > +{
-> > +	struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
-> > +	struct pci_epc *epc =3D ep->epc;
+> > +	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+> > +	struct pci_epc *epc = ep->epc;
 > > +	u16 msg_ctrl, msg_data;
 > > +	u32 msg_addr_lower, msg_addr_upper;
 > > +	u64 msg_addr;
@@ -43,19 +41,19 @@ map
 > > +
 > > +	/* Raise MSI per the PCI Local Bus Specification Revision 3.0,
 > 6.8.1. */
-> > +	msg_ctrl =3D dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
-> > +	has_upper =3D !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
-> > +	msg_addr_lower =3D dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
+> > +	msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+> > +	has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
+> > +	msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
 > > +	if (has_upper) {
-> > +		msg_addr_upper =3D dw_pcie_readl_dbi(pci,
+> > +		msg_addr_upper = dw_pcie_readl_dbi(pci,
 > MSI_MESSAGE_ADDR_U32);
-> > +		msg_data =3D dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
+> > +		msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
 > > +	} else {
-> > +		msg_addr_upper =3D 0;
-> > +		msg_data =3D dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
+> > +		msg_addr_upper = 0;
+> > +		msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
 > > +	}
-> > +	msg_addr =3D ((u64) msg_addr_upper) << 32 | msg_addr_lower;
-> > +	ret =3D dw_pcie_ep_map_addr(epc, ep->msi_mem_phys, msg_addr,
+> > +	msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+> > +	ret = dw_pcie_ep_map_addr(epc, ep->msi_mem_phys, msg_addr,
 > > +				  epc->mem->page_size);
 > > +	if (ret)
 > > +		return ret;
@@ -69,9 +67,8 @@ map
 > > +
 > >  void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 > >  {
-> >  	struct pci_epc *epc =3D ep->epc;
-> > diff --git a/drivers/pci/dwc/pcie-designware.h =
-b/drivers/pci/dwc/pcie-
+> >  	struct pci_epc *epc = ep->epc;
+> > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-
 > designware.h
 > > index 37dfad8d003f..24edac035160 100644
 > > --- a/drivers/pci/dwc/pcie-designware.h
@@ -85,14 +82,12 @@ b/drivers/pci/dwc/pcie-
 > >
 > >  /*
 > >   * Maximum number of MSI IRQs can be 256 per controller. But keep
-> > @@ -338,6 +340,7 @@ static inline int dw_pcie_host_init(struct =
-pcie_port
+> > @@ -338,6 +340,7 @@ static inline int dw_pcie_host_init(struct pcie_port
 > *pp)
 > >  void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
 > >  int dw_pcie_ep_init(struct dw_pcie_ep *ep);
 > >  void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
-> > +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 =
-interrupt_num);
+> > +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 interrupt_num);
 > >  void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
 > >  #else
 > >  static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
@@ -112,7 +107,7 @@ interrupt_num);
 > >  {
 > >  }
 > >
->=20
+> 
 > Acked-by: Joao Pinto <jpinto@synopsys.com>
 
 Acked-by: Jingoo Han <jingoohan1@gmail.com>
diff --git a/a/content_digest b/N1/content_digest
index ef36384..ed585d7 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -14,18 +14,16 @@
  "\00:1\0"
  "b\0"
  "On Wednesday, December 20, 2017 2:33 PM, Joao Pinto wrote:\n"
- ">=20\n"
- ">=20\n"
+ "> \n"
+ "> \n"
  "> Hi,\n"
- ">=20\n"
- "> =C3=80s 11:29 PM de 12/19/2017, Niklas Cassel escreveu:\n"
+ "> \n"
+ "> \303\200s 11:29 PM de 12/19/2017, Niklas Cassel escreveu:\n"
  "> > Add a generic function for raising MSI irqs that can be used by all\n"
  "> > DWC based controllers.\n"
  "> >\n"
- "> > Note that certain controllers, like DRA7xx, have a special =\n"
- "convenience\n"
- "> > register for raising MSI irqs that doesn't require you to explicitly =\n"
- "map\n"
+ "> > Note that certain controllers, like DRA7xx, have a special convenience\n"
+ "> > register for raising MSI irqs that doesn't require you to explicitly map\n"
  "> > the MSI address. Therefore, it is likely that certain drivers will\n"
  "> > not use this generic function, even if they can.\n"
  "> >\n"
@@ -41,15 +39,15 @@
  "> > index 700ed2f4becf..c5aa1cac5041 100644\n"
  "> > --- a/drivers/pci/dwc/pcie-designware-ep.c\n"
  "> > +++ b/drivers/pci/dwc/pcie-designware-ep.c\n"
- "> > @@ -282,6 +282,41 @@ static const struct pci_epc_ops epc_ops =3D {\n"
- "> >  \t.stop\t\t\t=3D dw_pcie_ep_stop,\n"
+ "> > @@ -282,6 +282,41 @@ static const struct pci_epc_ops epc_ops = {\n"
+ "> >  \t.stop\t\t\t= dw_pcie_ep_stop,\n"
  "> >  };\n"
  "> >\n"
  "> > +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,\n"
  "> > +\t\t\t     u8 interrupt_num)\n"
  "> > +{\n"
- "> > +\tstruct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);\n"
- "> > +\tstruct pci_epc *epc =3D ep->epc;\n"
+ "> > +\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n"
+ "> > +\tstruct pci_epc *epc = ep->epc;\n"
  "> > +\tu16 msg_ctrl, msg_data;\n"
  "> > +\tu32 msg_addr_lower, msg_addr_upper;\n"
  "> > +\tu64 msg_addr;\n"
@@ -58,19 +56,19 @@
  "> > +\n"
  "> > +\t/* Raise MSI per the PCI Local Bus Specification Revision 3.0,\n"
  "> 6.8.1. */\n"
- "> > +\tmsg_ctrl =3D dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);\n"
- "> > +\thas_upper =3D !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);\n"
- "> > +\tmsg_addr_lower =3D dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);\n"
+ "> > +\tmsg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);\n"
+ "> > +\thas_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);\n"
+ "> > +\tmsg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);\n"
  "> > +\tif (has_upper) {\n"
- "> > +\t\tmsg_addr_upper =3D dw_pcie_readl_dbi(pci,\n"
+ "> > +\t\tmsg_addr_upper = dw_pcie_readl_dbi(pci,\n"
  "> MSI_MESSAGE_ADDR_U32);\n"
- "> > +\t\tmsg_data =3D dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);\n"
+ "> > +\t\tmsg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);\n"
  "> > +\t} else {\n"
- "> > +\t\tmsg_addr_upper =3D 0;\n"
- "> > +\t\tmsg_data =3D dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);\n"
+ "> > +\t\tmsg_addr_upper = 0;\n"
+ "> > +\t\tmsg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);\n"
  "> > +\t}\n"
- "> > +\tmsg_addr =3D ((u64) msg_addr_upper) << 32 | msg_addr_lower;\n"
- "> > +\tret =3D dw_pcie_ep_map_addr(epc, ep->msi_mem_phys, msg_addr,\n"
+ "> > +\tmsg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;\n"
+ "> > +\tret = dw_pcie_ep_map_addr(epc, ep->msi_mem_phys, msg_addr,\n"
  "> > +\t\t\t\t  epc->mem->page_size);\n"
  "> > +\tif (ret)\n"
  "> > +\t\treturn ret;\n"
@@ -84,9 +82,8 @@
  "> > +\n"
  "> >  void dw_pcie_ep_exit(struct dw_pcie_ep *ep)\n"
  "> >  {\n"
- "> >  \tstruct pci_epc *epc =3D ep->epc;\n"
- "> > diff --git a/drivers/pci/dwc/pcie-designware.h =\n"
- "b/drivers/pci/dwc/pcie-\n"
+ "> >  \tstruct pci_epc *epc = ep->epc;\n"
+ "> > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-\n"
  "> designware.h\n"
  "> > index 37dfad8d003f..24edac035160 100644\n"
  "> > --- a/drivers/pci/dwc/pcie-designware.h\n"
@@ -100,14 +97,12 @@
  "> >\n"
  "> >  /*\n"
  "> >   * Maximum number of MSI IRQs can be 256 per controller. But keep\n"
- "> > @@ -338,6 +340,7 @@ static inline int dw_pcie_host_init(struct =\n"
- "pcie_port\n"
+ "> > @@ -338,6 +340,7 @@ static inline int dw_pcie_host_init(struct pcie_port\n"
  "> *pp)\n"
  "> >  void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);\n"
  "> >  int dw_pcie_ep_init(struct dw_pcie_ep *ep);\n"
  "> >  void dw_pcie_ep_exit(struct dw_pcie_ep *ep);\n"
- "> > +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 =\n"
- "interrupt_num);\n"
+ "> > +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 interrupt_num);\n"
  "> >  void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);\n"
  "> >  #else\n"
  "> >  static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)\n"
@@ -127,7 +122,7 @@
  "> >  {\n"
  "> >  }\n"
  "> >\n"
- ">=20\n"
+ "> \n"
  "> Acked-by: Joao Pinto <jpinto@synopsys.com>\n"
  "\n"
  "Acked-by: Jingoo Han <jingoohan1@gmail.com>\n"
@@ -135,4 +130,4 @@
  "Best regards,\n"
  Jingoo Han
 
-d07b4898be8ad4a26405acfaa2e98b55931e74d0b774d998b06697f37cd7ced8
+45107caa5b91b9360a1ba9f59e3a280a40e3ce7d6b916e307bd4853d30638daf

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