[PATCH 5/5] arm/perfevents: implement perf event support for ARMv6

[will.deacon@arm.com (Will Deacon)]

*Jamie Iles wrote:

> > That's exactly what I do for single core ARMv6. However, in the list of events
> > for mpcore I can't see any that wouldn't count. There's plenty of reserved
> > identifiers though so hopefully one of those will do the job. Also, ARM
> > counters can't be set to exclude any modes.
>
> Thinking about this a bit more, although we can't disable the counters, we can
> disable their interrupt reporting. So, when the generic perf events layer
> calls pmu->disable(event), we do the update of the event then turn off the
> IRQ. When we come to unthrottling, the counter will have carried on counting,
> but if we set the period again, the counter gets set with the correct restart
> value and then reenabled.

This was my first thought, but I was concerned about how it would play out
with the armpmu_read function. Now that I see we don't read disabled counters,
I can't see any reason not to simply disable the interrupt and stash the count
value.
 
> I think this should work for mpcore and is also required for the cycle counter
> on all v6 cores. I've given this a go using an artificially low period on a
> cycle counter and it does appear to do the job.

If we do this for mpcore, is it worth doing the same thing for the other v6 cores
too [and removing the ETM `hack']?

Cheers,

Will