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From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: Add support for the 16-way L310 L2 cache controller
Date: Thu, 29 Apr 2010 17:20:35 +0100	[thread overview]
Message-ID: <000701cae7b7$e61d45f0$b257d1d0$@deacon@arm.com> (raw)

Hi Jason,

The patch entitled `Add support for the 16-way L310 L2 cache controller'
which you submitted to RMK's patch system appears to perform a 16-way
invalidation even when the ways might not be present. This results in
writes to the reserved bits [15:8] of the invalidate-by-way ctrl register.

You can check the associativity by reading bit 16 of the auxiliary ctrl
register.

Will

             reply	other threads:[~2010-04-29 16:20 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-04-29 16:20 Will Deacon [this message]
2010-04-29 18:28 ` Add support for the 16-way L310 L2 cache controller Russell King - ARM Linux
     [not found] <3756028016583358140@unknownmsgid>
2010-04-30 17:17 ` Jason McMullan
     [not found] <-5319252541413655868@unknownmsgid>
2010-05-03 16:48 ` Jason McMullan

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