diff -urN vanilla-linux/Documentation/networking/s2io.txt vanilla-linux-patch/Documentation/networking/s2io.txt --- vanilla-linux/Documentation/networking/s2io.txt 1970-01-01 05:30:00.000000000 +0530 +++ vanilla-linux-patch/Documentation/networking/s2io.txt 2004-03-15 16:04:25.000000000 +0530 @@ -0,0 +1,48 @@ +S2IO Technologies XFrame 10 Gig adapter. +------------------------------------------- + +I. Module loadable parameters. +When loaded as a module, the driver provides a host of Module loadable +parameters, so the device can be tuned as per the users needs. +A list of the Module params is given below. +(i) ring_num: This can be used to program the number of + receive rings used in the driver. +(ii) ring_len: This defines the number of descriptors each ring + can have. There can be a maximum of 8 rings. +(iii) frame_len: This is an array of size 8. Using this we can + set the maximum size of the received frame that can + be steered into the corrsponding receive ring. +(iv) fifo_num: This defines the number of Tx FIFOs thats used in + the driver. +(v) fifo_len: Each element defines the number of + Tx descriptors that can be associated with each + corresponding FIFO. There are a maximum of 8 FIFOs. +(vi) tx_prio: This is a bool, if module is loaded with a non-zero + value for tx_prio multi FIFO scheme is activated. +(vii) rx_prio: This is a bool, if module is loaded with a non-zero + value for tx_prio multi RING scheme is activated. +(viii) latency_timer: The value given against this param will be + loaded into the latency timer register in PCI Config + space, else the register is left with its reset value. + +II. Performance tuning. + By changing a few sysctl parameters. + Copy the following lines into a file and run the following command, + "sysctl -p " +### IPV4 specific settings +net.ipv4.tcp_timestamps = 0 # turns TCP timestamp support off, default 1, reduces CPU use +net.ipv4.tcp_sack = 0 # turn SACK support off, default on +# on systems with a VERY fast bus -> memory interface this is the big gainer +net.ipv4.tcp_rmem = 10000000 10000000 10000000 # sets min/default/max TCP read buffer, default 4096 87380 174760 +net.ipv4.tcp_wmem = 10000000 10000000 10000000 # sets min/pressure/max TCP write buffer, default 4096 16384 131072 +net.ipv4.tcp_mem = 10000000 10000000 10000000 # sets min/pressure/max TCP buffer space, default 31744 32256 32768 + +### CORE settings (mostly for socket and UDP effect) +net.core.rmem_max = 524287 # maximum receive socket buffer size, default 131071 +net.core.wmem_max = 524287 # maximum send socket buffer size, default 131071 +net.core.rmem_default = 524287 # default receive socket buffer size, default 65535 +net.core.wmem_default = 524287 # default send socket buffer size, default 65535 +net.core.optmem_max = 524287 # maximum amount of option memory buffers, default 10240 +net.core.netdev_max_backlog = 300000 # number of unprocessed input packets before kernel starts dropping them, default 300 +---End of performance tuning file--- + diff -urN vanilla-linux/drivers/net/Kconfig vanilla-linux-patch/drivers/net/Kconfig --- vanilla-linux/drivers/net/Kconfig 2003-10-26 00:14:36.000000000 +0530 +++ vanilla-linux-patch/drivers/net/Kconfig 2004-02-27 20:26:00.000000000 +0530 @@ -2058,6 +2058,18 @@ bool "Use Rx Polling (NAPI) (EXPERIMENTAL)" depends on IXGB && EXPERIMENTAL +config S2IO + tristate "S2IO 10Gbe XFrame NIC" + depends on PCI + ---help--- + This driver supports the 10Gbe XFrame NIC of S2IO. + For help regarding driver compilation, installation and + tuning please look into ~/drivers/net/s2io/README.txt. + +config S2IO_NAPI + bool "Use Rx Polling (NAPI) (EXPERIMENTAL)" + depends on S2IO && EXPERIMENTAL + endmenu diff -urN vanilla-linux/drivers/net/s2io/Makefile vanilla-linux-patch/drivers/net/s2io/Makefile --- vanilla-linux/drivers/net/s2io/Makefile 1970-01-01 05:30:00.000000000 +0530 +++ vanilla-linux-patch/drivers/net/s2io/Makefile 2004-03-17 11:52:20.000000000 +0530 @@ -0,0 +1,5 @@ +# +# Makefile for the S2IO Technologies XFrame 10Gig NIC +# + +obj-$(CONFIG_S2IO) += s2io.o diff -urN vanilla-linux/drivers/net/s2io/regs.h vanilla-linux-patch/drivers/net/s2io/regs.h --- vanilla-linux/drivers/net/s2io/regs.h 1970-01-01 05:30:00.000000000 +0530 +++ vanilla-linux-patch/drivers/net/s2io/regs.h 2004-03-17 11:52:25.000000000 +0530 @@ -0,0 +1,775 @@ +/************************************************************************ + * regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC + * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com) + + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + * Drivers based on or derived from this code fall under the GPL and must + * retain the authorship, copyright and license notice. This file is not + * a complete program and may only be used when the entire operating + * system is licensed under the GPL. + * See the file COPYING in this distribution for more information. + ************************************************************************/ +#ifndef _REGS_H +#define _REGS_H + +#define TBD 0 + +typedef struct _XENA_dev_config { +/* Convention: mHAL_XXX is mask, vHAL_XXX is value */ + +/* General Control-Status Registers */ + u64 general_int_status; +#define GEN_INTR_TXPIC BIT(0) +#define GEN_INTR_TXDMA BIT(1) +#define GEN_INTR_TXMAC BIT(2) +#define GEN_INTR_TXXGXS BIT(3) +#define GEN_INTR_TXTRAFFIC BIT(8) +#define GEN_INTR_RXPIC BIT(32) +#define GEN_INTR_RXDMA BIT(33) +#define GEN_INTR_RXMAC BIT(34) +#define GEN_INTR_MC BIT(35) +#define GEN_INTR_RXXGXS BIT(36) +#define GEN_INTR_RXTRAFFIC BIT(40) +#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \ + GEN_INTR_TXDMA | GEN_INTR_RXDMA | \ + GEN_INTR_TXMAC | GEN_INTR_RXMAC | \ + GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \ + GEN_INTR_MC + + u64 general_int_mask; + + u8 unused0[0x100 - 0x10]; + + u64 sw_reset; +/* XGXS must be removed from reset only once. */ +#define SW_RESET_XENA vBIT(0xA5,0,8) +#define SW_RESET_FLASH vBIT(0xA5,8,8) +#define SW_RESET_EOI vBIT(0xA5,16,8) +#define SW_RESET_ALL (SW_RESET_XENA | \ + SW_RESET_FLASH | \ + SW_RESET_EOI) +/* The SW_RESET register must read this value after a successful reset. */ +#define SW_RESET_RAW_VAL 0xA5000000 + + + u64 adapter_status; +#define ADAPTER_STATUS_TDMA_READY BIT(0) +#define ADAPTER_STATUS_RDMA_READY BIT(1) +#define ADAPTER_STATUS_PFC_READY BIT(2) +#define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) +#define ADAPTER_STATUS_PIC_QUIESCENT BIT(5) +#define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) +#define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) +#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) +#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) +#define ADAPTER_STATUS_MC_DRAM_READY BIT(24) +#define ADAPTER_STATUS_MC_QUEUES_READY BIT(25) +#define ADAPTER_STATUS_M_PLL_LOCK BIT(30) +#define ADAPTER_STATUS_P_PLL_LOCK BIT(31) + + u64 adapter_control; +#define ADAPTER_CNTL_EN BIT(7) +#define ADAPTER_EOI_TX_ON BIT(15) +#define ADAPTER_LED_ON BIT(23) +#define ADAPTER_UDPI(val) vBIT(val,36,4) +#define ADAPTER_WAIT_INT BIT(48) +#define ADAPTER_ECC_EN BIT(55) + + u64 serr_source; +#define SERR_SOURCE_PIC BIT(0) +#define SERR_SOURCE_TXDMA BIT(1) +#define SERR_SOURCE_RXDMA BIT(2) +#define SERR_SOURCE_MAC BIT(3) +#define SERR_SOURCE_MC BIT(4) +#define SERR_SOURCE_XGXS BIT(5) +#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ + SERR_SOURCE_TXDMA | \ + SERR_SOURCE_RXDMA | \ + SERR_SOURCE_MAC | \ + SERR_SOURCE_MC | \ + SERR_SOURCE_XGXS) + + + u8 unused_0[0x800 - 0x120]; + +/* PCI-X Controller registers */ + u64 pic_int_status; + u64 pic_int_mask; +#define PIC_INT_TX BIT(0) +#define PIC_INT_FLSH BIT(1) +#define PIC_INT_MDIO BIT(2) +#define PIC_INT_IIC BIT(3) +#define PIC_INT_GPIO BIT(4) +#define PIC_INT_RX BIT(32) + + u64 txpic_int_reg; + u64 txpic_int_mask; +#define PCIX_INT_REG_ECC_SG_ERR BIT(0) +#define PCIX_INT_REG_ECC_DB_ERR BIT(1) +#define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) +#define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) +#define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) +#define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) +#define PCIX_INT_REG_TRT_FSM_SERR BIT(13) +#define PCIX_INT_REG_SRT_FSM_SERR BIT(14) +#define PCIX_INT_REG_PIFR_FSM_SERR BIT(15) +#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) +#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) +#define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) +#define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) +/* +#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) +#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) +#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) +*/ + u64 txpic_alarms; + u64 rxpic_int_reg; + u64 rxpic_int_mask; + u64 rxpic_alarms; + + u64 flsh_int_reg; + u64 flsh_int_mask; +#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) +#define PIC_FLSH_INT_REG_ERR BIT(62) + u64 flash_alarms; + + u64 mdio_int_reg; + u64 mdio_int_mask; +#define MDIO_INT_REG_MDIO_BUS_ERR BIT(0) +#define MDIO_INT_REG_DTX_BUS_ERR BIT(8) +#define MDIO_INT_REG_LASI BIT(39) + u64 mdio_alarms; + + u64 iic_int_reg; + u64 iic_int_mask; +#define IIC_INT_REG_BUS_FSM_ERR BIT(4) +#define IIC_INT_REG_BIT_FSM_ERR BIT(5) +#define IIC_INT_REG_CYCLE_FSM_ERR BIT(6) +#define IIC_INT_REG_REQ_FSM_ERR BIT(7) +#define IIC_INT_REG_ACK_ERR BIT(8) + u64 iic_alarms; + + u8 unused4[0x08]; + + u64 gpio_int_reg; + u64 gpio_int_mask; + u64 gpio_alarms; + + u8 unused5[0x38]; + + u64 tx_traffic_int; +#define TX_TRAFFIC_INT_n(n) BIT(n) + u64 tx_traffic_mask; + + u64 rx_traffic_int; +#define RX_TRAFFIC_INT_n(n) BIT(n) + u64 rx_traffic_mask; + +/* PIC Control registers */ + u64 pic_control; +#define PIC_CNTL_RX_ALARM_MAP_1 BIT(0) +#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4) + + u64 swapper_ctrl; +#define SWAPPER_CTRL_PIF_R_FE BIT(0) +#define SWAPPER_CTRL_PIF_R_SE BIT(1) +#define SWAPPER_CTRL_PIF_W_FE BIT(8) +#define SWAPPER_CTRL_PIF_W_SE BIT(9) +#define SWAPPER_CTRL_TXP_FE BIT(16) +#define SWAPPER_CTRL_TXP_SE BIT(17) +#define SWAPPER_CTRL_TXD_R_FE BIT(18) +#define SWAPPER_CTRL_TXD_R_SE BIT(19) +#define SWAPPER_CTRL_TXD_W_FE BIT(20) +#define SWAPPER_CTRL_TXD_W_SE BIT(21) +#define SWAPPER_CTRL_TXF_R_FE BIT(22) +#define SWAPPER_CTRL_TXF_R_SE BIT(23) +#define SWAPPER_CTRL_RXD_R_FE BIT(32) +#define SWAPPER_CTRL_RXD_R_SE BIT(33) +#define SWAPPER_CTRL_RXD_W_FE BIT(34) +#define SWAPPER_CTRL_RXD_W_SE BIT(35) +#define SWAPPER_CTRL_RXF_W_FE BIT(36) +#define SWAPPER_CTRL_RXF_W_SE BIT(37) +#define SWAPPER_CTRL_XMSI_FE BIT(40) +#define SWAPPER_CTRL_XMSI_SE BIT(41) +#define SWAPPER_CTRL_STATS_FE BIT(48) +#define SWAPPER_CTRL_STATS_SE BIT(49) + + u64 pif_rd_swapper_fb; +#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF + + u64 scheduled_int_ctrl; +#define SCHED_INT_CTRL_TIMER_EN BIT(0) +#define SCHED_INT_CTRL_ONE_SHOT BIT(1) +#define SCHED_INT_CTRL_INT2MSI TBD +#define SCHED_INT_PERIOD TBD + + u64 txreqtimeout; +#define TXREQTO_VAL(val) vBIT(val,0,32) +#define TXREQTO_EN BIT(63) + + u64 statsreqtimeout; +#define STATREQTO_VAL(n) TBD +#define STATREQTO_EN BIT(63) + + u64 read_retry_delay; + u64 read_retry_acceleration; + u64 write_retry_delay; + u64 write_retry_acceleration; + + u64 xmsi_control; + u64 xmsi_access; + u64 xmsi_address; + u64 xmsi_data; + + u64 rx_mat; + + u8 unused6[0x8]; + + u64 tx_mat0_7; + u64 tx_mat8_15; + u64 tx_mat16_23; + u64 tx_mat24_31; + u64 tx_mat32_39; + u64 tx_mat40_47; + u64 tx_mat48_55; + u64 tx_mat56_63; + + u8 unused_1[0x10]; + + /* Automated statistics collection */ + u64 stat_cfg; +#define STAT_CFG_STAT_EN BIT(0) +#define STAT_CFG_ONE_SHOT_EN BIT(1) +#define STAT_CFG_STAT_NS_EN BIT(8) +#define STAT_CFG_STAT_RO BIT(9) +#define STAT_TRSF_PER(n) TBD +#define PER_SEC 0x208d5 +#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32) + + u64 stat_addr; + + /* General Configuration */ + u64 mdio_control; + + u64 dtx_control; + + u64 i2c_control; +#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) +#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) +#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) +#define I2C_CONTROL_READ BIT(24) +#define I2C_CONTROL_NACK BIT(25) +#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4) +#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) +#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) +#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) + + u64 gpio_control; +#define GPIO_CTRL_GPIO_0 BIT(8) + + u8 unused7[0x600]; + +/* TxDMA registers */ + u64 txdma_int_status; + u64 txdma_int_mask; +#define TXDMA_PFC_INT BIT(0) +#define TXDMA_TDA_INT BIT(1) +#define TXDMA_PCC_INT BIT(2) +#define TXDMA_TTI_INT BIT(3) +#define TXDMA_LSO_INT BIT(4) +#define TXDMA_TPA_INT BIT(5) +#define TXDMA_SM_INT BIT(6) + u64 pfc_err_reg; + u64 pfc_err_mask; + u64 pfc_err_alarm; + + u64 tda_err_reg; + u64 tda_err_mask; + u64 tda_err_alarm; + + u64 pcc_err_reg; + u64 pcc_err_mask; + u64 pcc_err_alarm; + + u64 tti_err_reg; + u64 tti_err_mask; + u64 tti_err_alarm; + + u64 lso_err_reg; + u64 lso_err_mask; + u64 lso_err_alarm; + + u64 tpa_err_reg; + u64 tpa_err_mask; + u64 tpa_err_alarm; + + u64 sm_err_reg; + u64 sm_err_mask; + u64 sm_err_alarm; + + u8 unused8[0x100 - 0xB8]; + +/* TxDMA arbiter */ + u64 tx_dma_wrap_stat; + +/* Tx FIFO controller */ +#define X_MAX_FIFOS 8 +#define X_FIFO_MAX_LEN 0x1FFF /*8191 */ + u64 tx_fifo_partition_0; +#define TX_FIFO_PARTITION_EN BIT(0) +#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) +#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) +#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) +#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) + + u64 tx_fifo_partition_1; +#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) +#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) +#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) +#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) + + u64 tx_fifo_partition_2; +#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) +#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) +#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) +#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) + + u64 tx_fifo_partition_3; +#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) +#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) +#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) +#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) + +#define TX_FIFO_PARTITION_PRI_0 0 /* highest */ +#define TX_FIFO_PARTITION_PRI_1 1 +#define TX_FIFO_PARTITION_PRI_2 2 +#define TX_FIFO_PARTITION_PRI_3 3 +#define TX_FIFO_PARTITION_PRI_4 4 +#define TX_FIFO_PARTITION_PRI_5 5 +#define TX_FIFO_PARTITION_PRI_6 6 +#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */ + + u64 tx_w_round_robin_0; + u64 tx_w_round_robin_1; + u64 tx_w_round_robin_2; + u64 tx_w_round_robin_3; + u64 tx_w_round_robin_4; + + u64 tti_command_mem; +#define TTI_CMD_MEM_WE BIT(7) +#define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) +#define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) +#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) + + u64 tti_data1_mem; +#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) +#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) +#define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) +#define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) +#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) +#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) +#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) + + u64 tti_data2_mem; +#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) +#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) +#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) +#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) + +/* Tx Protocol assist */ + u64 tx_pa_cfg; +#define TX_PA_CFG_IGNORE_FRM_ERR BIT(1) +#define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) +#define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) +#define TX_PA_CFG_IGNORE_L2_ERR BIT(6) + +/* Recent add, used only debug purposes. */ + u64 pcc_enable; + + u8 unused9[0x700 - 0x178]; + + u64 txdma_debug_ctrl; + + u8 unused10[0x1800 - 0x1708]; + +/* RxDMA Registers */ + u64 rxdma_int_status; + u64 rxdma_int_mask; +#define RXDMA_INT_RC_INT_M BIT(0) +#define RXDMA_INT_RPA_INT_M BIT(1) +#define RXDMA_INT_RDA_INT_M BIT(2) +#define RXDMA_INT_RTI_INT_M BIT(3) + + u64 rda_err_reg; + u64 rda_err_mask; + u64 rda_err_alarm; + + u64 rc_err_reg; + u64 rc_err_mask; + u64 rc_err_alarm; + + u64 prc_pcix_err_reg; + u64 prc_pcix_err_mask; + u64 prc_pcix_err_alarm; + + u64 rpa_err_reg; + u64 rpa_err_mask; + u64 rpa_err_alarm; + + u64 rti_err_reg; + u64 rti_err_mask; + u64 rti_err_alarm; + + u8 unused11[0x100 - 0x88]; + +/* DMA arbiter */ + u64 rx_queue_priority; +#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) +#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) +#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) +#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) +#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) +#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) +#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) +#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) + +#define RX_QUEUE_PRI_0 0 /* highest */ +#define RX_QUEUE_PRI_1 1 +#define RX_QUEUE_PRI_2 2 +#define RX_QUEUE_PRI_3 3 +#define RX_QUEUE_PRI_4 4 +#define RX_QUEUE_PRI_5 5 +#define RX_QUEUE_PRI_6 6 +#define RX_QUEUE_PRI_7 7 /* lowest */ + + u64 rx_w_round_robin_0; + u64 rx_w_round_robin_1; + u64 rx_w_round_robin_2; + u64 rx_w_round_robin_3; + u64 rx_w_round_robin_4; + + /* Per-ring controller regs */ +#define RX_MAX_RINGS 8 +#if 0 +#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */ +#define RX_MIN_RINGS_SZ 0x3F /* 63 */ +#endif + u64 prc_rxd0_n[RX_MAX_RINGS]; + u64 prc_ctrl_n[RX_MAX_RINGS]; +#define PRC_CTRL_RC_ENABLED BIT(7) +#define PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) +#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2) +#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2) +#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2) +#define PRC_CTRL_RING_MODE_x vBIT(3,14,2) +#define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23)) +#define PRC_CTRL_NO_SNOOP_DESC BIT(22) +#define PRC_CTRL_NO_SNOOP_BUFF BIT(23) +#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) + + u64 prc_alarm_action; +#define PRC_ALARM_ACTION_RR_R0_STOP BIT(3) +#define PRC_ALARM_ACTION_RW_R0_STOP BIT(7) +#define PRC_ALARM_ACTION_RR_R1_STOP BIT(11) +#define PRC_ALARM_ACTION_RW_R1_STOP BIT(15) +#define PRC_ALARM_ACTION_RR_R2_STOP BIT(19) +#define PRC_ALARM_ACTION_RW_R2_STOP BIT(23) +#define PRC_ALARM_ACTION_RR_R3_STOP BIT(27) +#define PRC_ALARM_ACTION_RW_R3_STOP BIT(31) +#define PRC_ALARM_ACTION_RR_R4_STOP BIT(35) +#define PRC_ALARM_ACTION_RW_R4_STOP BIT(39) +#define PRC_ALARM_ACTION_RR_R5_STOP BIT(43) +#define PRC_ALARM_ACTION_RW_R5_STOP BIT(47) +#define PRC_ALARM_ACTION_RR_R6_STOP BIT(51) +#define PRC_ALARM_ACTION_RW_R6_STOP BIT(55) +#define PRC_ALARM_ACTION_RR_R7_STOP BIT(59) +#define PRC_ALARM_ACTION_RW_R7_STOP BIT(63) + +/* Receive traffic interrupts */ + u64 rti_command_mem; +#define RTI_CMD_MEM_WE BIT(7) +#define RTI_CMD_MEM_STROBE BIT(15) +#define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) +#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) +#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) + + u64 rti_data1_mem; +#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) +#define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) +#define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) +#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) +#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) +#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) + + u64 rti_data2_mem; +#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) +#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) +#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) +#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) + + u64 rx_pa_cfg; +#define RX_PA_CFG_IGNORE_FRM_ERR BIT(1) +#define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) +#define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) + + u8 unused12[0x700 - 0x1D8]; + + u64 rxdma_debug_ctrl; + + u8 unused13[0x2000 - 0x1f08]; + +/* Media Access Controller Register */ + u64 mac_int_status; + u64 mac_int_mask; +#define MAC_INT_STATUS_TMAC_INT BIT(0) +#define MAC_INT_STATUS_RMAC_INT BIT(1) + + u64 mac_tmac_err_reg; +#define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15) +#define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23) +#define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31) + u64 mac_tmac_err_mask; + u64 mac_tmac_err_alarm; + + u64 mac_rmac_err_reg; +#define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0) +#define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14) +#define RMAC_ERR_REG_ECC_DB_ERR BIT(15) +#define RMAC_LINK_STATE_CHANGE_INT BIT(31) + u64 mac_rmac_err_mask; + u64 mac_rmac_err_alarm; + + u8 unused14[0x100 - 0x40]; + + u64 mac_cfg; +#define MAC_CFG_TMAC_ENABLE BIT(0) +#define MAC_CFG_RMAC_ENABLE BIT(1) +#define MAC_CFG_LAN_NOT_WAN BIT(2) +#define MAC_CFG_TMAC_LOOPBACK BIT(3) +#define MAC_CFG_TMAC_APPEND_PAD BIT(4) +#define MAC_CFG_RMAC_STRIP_FCS BIT(5) +#define MAC_CFG_RMAC_STRIP_PAD BIT(6) +#define MAC_CFG_RMAC_PROM_ENABLE BIT(7) +#define MAC_RMAC_DISCARD_PFRM BIT(8) +#define MAC_RMAC_BCAST_ENABLE BIT(9) +#define MAC_RMAC_ALL_ADDR_ENABLE BIT(10) +#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) + + u64 tmac_avg_ipg; +#define TMAC_AVG_IPG(val) vBIT(val,0,8) + + u64 rmac_max_pyld_len; +#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) +#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14) +#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14) + + u64 rmac_err_cfg; +#define RMAC_ERR_FCS BIT(0) +#define RMAC_ERR_FCS_ACCEPT BIT(1) +#define RMAC_ERR_TOO_LONG BIT(1) +#define RMAC_ERR_TOO_LONG_ACCEPT BIT(1) +#define RMAC_ERR_RUNT BIT(2) +#define RMAC_ERR_RUNT_ACCEPT BIT(2) +#define RMAC_ERR_LEN_MISMATCH BIT(3) +#define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) + + u64 rmac_cfg_key; +#define RMAC_CFG_KEY(val) vBIT(val,0,16) + +#define MAX_MAC_ADDRESSES 16 +#define MAX_MC_ADDRESSES 32 /* Multicast addresses */ +#define MAC_MAC_ADDR_START_OFFSET 0 +#define MAC_MC_ADDR_START_OFFSET 16 +#define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */ + u64 rmac_addr_cmd_mem; +#define RMAC_ADDR_CMD_MEM_WE BIT(7) +#define RMAC_ADDR_CMD_MEM_RD 0 +#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) +#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) +#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) + + u64 rmac_addr_data0_mem; +#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) +#define RMAC_ADDR_DATA0_MEM_USER BIT(48) + + u64 rmac_addr_data1_mem; +#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) + + u8 unused15[0x8]; + +/* + u64 rmac_addr_cfg; +#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) +#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) +#define RMAC_ADDR_BCAST_EN vBIT(0)_48 +#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 +*/ + u64 tmac_ipg_cfg; + + u64 rmac_pause_cfg; +#define RMAC_PAUSE_GEN BIT(0) +#define RMAC_PAUSE_GEN_ENABLE BIT(0) +#define RMAC_PAUSE_RX BIT(1) +#define RMAC_PAUSE_RX_ENABLE BIT(1) +#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) +#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) + + u64 rmac_red_cfg; + + u64 rmac_red_rate_q0q3; + u64 rmac_red_rate_q4q7; + + u64 mac_link_util; +#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7) +#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) +#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) +#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7) +#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) +#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) + +#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \ + MAC_RX_LINK_UTIL_DISABLE + + u64 rmac_invalid_ipg; + +/* rx traffic steering */ +#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) + u64 rts_frm_len_n[8]; + + u64 rts_qos_steering; + +#define MAX_DIX_MAP 4 + u64 rts_dix_map_n[MAX_DIX_MAP]; +#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) +#define RTS_DIX_MAP_SCW(val) BIT(val,21) + + u64 rts_q_alternates; + u64 rts_default_q; + + u64 rts_ctrl; +#define RTS_CTRL_IGNORE_SNAP_OUI BIT(2) +#define RTS_CTRL_IGNORE_LLC_CTRL BIT(3) + + u64 rts_pn_cam_ctrl; +#define RTS_PN_CAM_CTRL_WE BIT(7) +#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) +#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) +#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) + u64 rts_pn_cam_data; +#define RTS_PN_CAM_DATA_TCP_SELECT BIT(7) +#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) +#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) + + u64 rts_ds_mem_ctrl; +#define RTS_DS_MEM_CTRL_WE BIT(7) +#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) +#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) +#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) + u64 rts_ds_mem_data; +#define RTS_DS_MEM_DATA(n) vBIT(n,0,8) + + u8 unused16[0x700 - 0x220]; + + u64 mac_debug_ctrl; +#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL + + u8 unused17[0x2800 - 0x2708]; + +/* memory controller registers */ + u64 mc_int_status; +#define MC_INT_STATUS_MC_INT BIT(0) + u64 mc_int_mask; +#define MC_INT_MASK_MC_INT BIT(0) + + u64 mc_err_reg; +#define MC_ERR_REG_ECC_DB_ERR_L BIT(14) +#define MC_ERR_REG_ECC_DB_ERR_U BIT(15) +#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) +#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) +#define MC_ERR_REG_SM_ERR BIT(31) + u64 mc_err_mask; + u64 mc_err_alarm; + + u8 unused18[0x100 - 0x28]; + +/* MC configuration */ + u64 rx_queue_cfg; +#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) +#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) +#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) +#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) +#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) +#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) +#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) +#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) + + u64 mc_rldram_mrs; +#define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) +#define MC_RLDRAM_MRS_ENABLE BIT(47) + + u64 mc_rldram_interleave; + + u64 mc_pause_thresh_q0q3; + u64 mc_pause_thresh_q4q7; + + u64 mc_red_thresh_q[8]; + + u8 unused19[0x200 - 0x168]; + u64 mc_rldram_ref_per; + u8 unused20[0x220 - 0x208]; + u64 mc_rldram_test_ctrl; +#define MC_RLDRAM_TEST_MODE BIT(47) +#define MC_RLDRAM_TEST_WRITE BIT(7) +#define MC_RLDRAM_TEST_GO BIT(15) +#define MC_RLDRAM_TEST_DONE BIT(23) +#define MC_RLDRAM_TEST_PASS BIT(31) + + u8 unused21[0x240 - 0x228]; + u64 mc_rldram_test_add; + u8 unused22[0x260 - 0x248]; + u64 mc_rldram_test_d0; + u8 unused23[0x280 - 0x268]; + u64 mc_rldram_test_d1; + u8 unused24[0x300 - 0x288]; + u64 mc_rldram_test_d2; + u8 unused25[0x700 - 0x308]; + u64 mc_debug_ctrl; + + u8 unused26[0x3000 - 0x2f08]; + +/* XGXG */ + /* XGXS control registers */ + + u64 xgxs_int_status; +#define XGXS_INT_STATUS_TXGXS BIT(0) +#define XGXS_INT_STATUS_RXGXS BIT(1) + u64 xgxs_int_mask; +#define XGXS_INT_MASK_TXGXS BIT(0) +#define XGXS_INT_MASK_RXGXS BIT(1) + + u64 xgxs_txgxs_err_reg; +#define TXGXS_ECC_DB_ERR BIT(15) + u64 xgxs_txgxs_err_mask; + u64 xgxs_txgxs_err_alarm; + + u64 xgxs_rxgxs_err_reg; + u64 xgxs_rxgxs_err_mask; + u64 xgxs_rxgxs_err_alarm; + + u8 unused27[0x100 - 0x40]; + + u64 xgxs_cfg; + u64 xgxs_status; + + u64 xgxs_cfg_key; + u64 xgxs_efifo_cfg; /* CHANGED */ + u64 rxgxs_ber_0; /* CHANGED */ + u64 rxgxs_ber_1; /* CHANGED */ + +} XENA_dev_config_t; + +#define XENA_REG_SPACE sizeof(XENA_dev_config_t) +#define XENA_EEPROM_SPACE (0x01 << 11) + +#endif /* _REGS_H */ diff -urN vanilla-linux/drivers/net/s2io/s2io.c vanilla-linux-patch/drivers/net/s2io/s2io.c --- vanilla-linux/drivers/net/s2io/s2io.c 1970-01-01 05:30:00.000000000 +0530 +++ vanilla-linux-patch/drivers/net/s2io/s2io.c 2004-03-18 18:00:12.000000000 +0530 @@ -0,0 +1,4389 @@ +/************************************************************************ + * s2io.c: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC + * Copyright(c) 2002-2005 S2IO Technologies + + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + * Drivers based on or derived from this code fall under the GPL and must + * retain the authorship, copyright and license notice. This file is not + * a complete program and may only be used when the entire operating + * system is licensed under the GPL. + * See the file COPYING in this distribution for more information. + * + * Credits: + * Jeff Garzik : For pointing out the improper error condition + * check in the s2io_xmit routine and also some + * issues in the Tx watch dog function. Also for + * patiently answering all those innumerable + * questions regaring the 2.6 porting issues. + * Stephen Hemminger : Providing proper 2.6 porting mechanism for some + * macros available only in 2.6 Kernel. + * Francois Romieu : For pointing out all code part that were + * deprecated and also styling related comments. + * Grant Grundler : For helping me get rid of some Architecture + * dependent code. + * Christopher Hellwig : Some more 2.6 specific issues in the driver. + * + * The module loadable parameters that are supported by the driver and a brief + * explaination of all the variables. + * ring_num : This can be used to program the number of receive rings used + * in the driver. + * frame_len: This is an array of size 8. Using this we can set the maximum + * size of the received frame that can be steered into the corrsponding + * receive ring. + * ring_len: This defines the number of descriptors each ring can have. This + * is also an array of size 8. + * fifo_num: This defines the number of Tx FIFOs thats used int the driver. + * fifo_len: This too is an array of 8. Each element defines the number of + * Tx descriptors that can be associated with each corresponding FIFO. + * latency_timer: This input is programmed into the Latency timer register + * in PCI Configuration space. + ************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* local include */ +#include "s2io.h" +#include "regs.h" + +/* S2io Driver name & version. */ +static char s2io_driver_name[] = "s2io"; +static char s2io_driver_version[] = "Version 1.0"; + +#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ + ADAPTER_STATUS_RMAC_LOCAL_FAULT))) +#define TASKLET_IN_USE test_and_set_bit(0, \ + (unsigned long *)(&sp->tasklet_status)) +#define PANIC 1 +#define LOW 2 +static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring) +{ + int level = 0; + if ((sp->pkt_cnt[ring] - rxb_size) > 128) { + level = LOW; + if (rxb_size < sp->pkt_cnt[ring] / 8) + level = PANIC; + } + + return level; +} + +/* Ethtool related variables and Macros. */ +static char s2io_gstrings[][ETH_GSTRING_LEN] = { + "Register test\t(offline)", + "Eeprom test\t(offline)", + "Link test\t(online)", + "RLDRAM test\t(offline)", + "BIST Test\t(offline)" +}; + +static char ethtool_stats_keys[][ETH_GSTRING_LEN] = { + {"tmac_frms"}, + {"tmac_data_octets"}, + {"tmac_drop_frms"}, + {"tmac_mcst_frms"}, + {"tmac_bcst_frms"}, + {"tmac_pause_ctrl_frms"}, + {"tmac_any_err_frms"}, + {"tmac_vld_ip_octets"}, + {"tmac_vld_ip"}, + {"tmac_drop_ip"}, + {"tmac_icmp"}, + {"tmac_rst_tcp"}, + {"tmac_tcp"}, + {"tmac_udp"}, + {"rmac_vld_frms"}, + {"rmac_data_octets"}, + {"rmac_fcs_err_frms"}, + {"rmac_drop_frms"}, + {"rmac_vld_mcst_frms"}, + {"rmac_vld_bcst_frms"}, + {"rmac_in_rng_len_err_frms"}, + {"rmac_long_frms"}, + {"rmac_pause_ctrl_frms"}, + {"rmac_discarded_frms"}, + {"rmac_usized_frms"}, + {"rmac_osized_frms"}, + {"rmac_frag_frms"}, + {"rmac_jabber_frms"}, + {"rmac_ip"}, + {"rmac_ip_octets"}, + {"rmac_hdr_err_ip"}, + {"rmac_drop_ip"}, + {"rmac_icmp"}, + {"rmac_tcp"}, + {"rmac_udp"}, + {"rmac_err_drp_udp"}, + {"rmac_pause_cnt"}, + {"rmac_accepted_ip"}, + {"rmac_err_tcp"}, +}; + +#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN +#define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN + +#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN +#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN + + +/* Constants to be programmed into the Xena's registers to configure + * the XAUI. + */ + +#define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL +#define END_SIGN 0x0 + +static u64 default_mdio_cfg[] = { + /* Reset PMA PLL */ + 0xC001010000000000ULL, 0xC0010100000000E0ULL, + 0xC0010100008000E4ULL, + /* Remove Reset from PMA PLL */ + 0xC001010000000000ULL, 0xC0010100000000E0ULL, + 0xC0010100000000E4ULL, + END_SIGN +}; + +static u64 default_dtx_cfg[] = { + 0x8000051500000000ULL, 0x80000515000000E0ULL, + 0x80000515D93500E4ULL, 0x8001051500000000ULL, + 0x80010515000000E0ULL, 0x80010515001E00E4ULL, + 0x8002051500000000ULL, 0x80020515000000E0ULL, + 0x80020515F21000E4ULL, + /* Set PADLOOPBACKN */ + 0x8002051500000000ULL, 0x80020515000000E0ULL, + 0x80020515B20000E4ULL, 0x8003051500000000ULL, + 0x80030515000000E0ULL, 0x80030515B20000E4ULL, + 0x8004051500000000ULL, 0x80040515000000E0ULL, + 0x80040515B20000E4ULL, 0x8005051500000000ULL, + 0x80050515000000E0ULL, 0x80050515B20000E4ULL, + SWITCH_SIGN, + /* Remove PADLOOPBACKN */ + 0x8002051500000000ULL, 0x80020515000000E0ULL, + 0x80020515F20000E4ULL, 0x8003051500000000ULL, + 0x80030515000000E0ULL, 0x80030515F20000E4ULL, + 0x8004051500000000ULL, 0x80040515000000E0ULL, + 0x80040515F20000E4ULL, 0x8005051500000000ULL, + 0x80050515000000E0ULL, 0x80050515F20000E4ULL, + END_SIGN +}; + +/* Constants for Fixing the MacAddress problem seen mostly on + * Alpha machines. + */ +static u64 fix_mac[] = { + 0x0060000000000000ULL, 0x0060600000000000ULL, + 0x0040600000000000ULL, 0x0000600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0000600000000000ULL, + 0x0040600000000000ULL, 0x0060600000000000ULL, + END_SIGN +}; + + +/* Module Loadable parameters. */ +static u32 ring_num; +static u32 frame_len[MAX_RX_RINGS]; +static u32 ring_len[MAX_RX_RINGS]; +static u32 fifo_num; +static u32 fifo_len[MAX_TX_FIFOS]; +static u32 rx_prio; +static u32 tx_prio; +static u8 latency_timer = 0; + +/* + * S2IO device table. + * This table lists all the devices that this driver supports. + */ +static struct pci_device_id s2io_tbl[] __devinitdata = { + {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN, + PCI_ANY_ID, PCI_ANY_ID}, + {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI, + PCI_ANY_ID, PCI_ANY_ID}, + {0,} +}; + +MODULE_DEVICE_TABLE(pci, s2io_tbl); + +static struct pci_driver s2io_driver = { + name:"S2IO", + id_table:s2io_tbl, + probe:s2io_init_nic, + remove:s2io_rem_nic, +}; + +/* + * Input Arguments: + * Device private variable. + * Return Value: + * SUCCESS on success and an appropriate -ve value on failure. + * Description: + * The function allocates the all memory areas shared + * between the NIC and the driver. This includes Tx descriptors, + * Rx descriptors and the statistics block. + */ +static int initSharedMem(struct s2io_nic *nic) +{ + u32 size; + void *tmp_v_addr, *tmp_v_addr_next; + dma_addr_t tmp_p_addr, tmp_p_addr_next; + RxD_block_t *pre_rxd_blk = NULL; + int i, j, blk_cnt; + struct net_device *dev = nic->dev; + + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &nic->mac_control; + config = &nic->config; + + + /* Allocation and initialization of TXDLs in FIOFs */ + size = 0; + for (i = 0; i < config->TxFIFONum; i++) { + size += config->TxCfg[i].FifoLen; + } + if (size > MAX_AVAILABLE_TXDS) { + DBG_PRINT(ERR_DBG, "%s: Total number of Tx FIFOs ", + dev->name); + DBG_PRINT(ERR_DBG, "exceeds the maximum value "); + DBG_PRINT(ERR_DBG, "that can be used\n"); + return FAILURE; + } + size *= (sizeof(TxD_t) * config->MaxTxDs); + + mac_control->txd_list_mem = pci_alloc_consistent + (nic->pdev, size, &mac_control->txd_list_mem_phy); + if (!mac_control->txd_list_mem) { + return -ENOMEM; + } + mac_control->txd_list_mem_sz = size; + + tmp_v_addr = mac_control->txd_list_mem; + tmp_p_addr = mac_control->txd_list_mem_phy; + memset(tmp_v_addr, 0, size); + + DBG_PRINT(INIT_DBG, "%s:List Mem PHY: 0x%llx\n", dev->name, + (unsigned long long) tmp_p_addr); + + for (i = 0; i < config->TxFIFONum; i++) { + mac_control->txdl_start_phy[i] = tmp_p_addr; + mac_control->txdl_start[i] = (TxD_t *) tmp_v_addr; + mac_control->tx_curr_put_info[i].offset = 0; + mac_control->tx_curr_put_info[i].fifo_len = + config->TxCfg[i].FifoLen - 1; + mac_control->tx_curr_get_info[i].offset = 0; + mac_control->tx_curr_get_info[i].fifo_len = + config->TxCfg[i].FifoLen - 1; + + tmp_p_addr += + (config->TxCfg[i].FifoLen * (sizeof(TxD_t)) * + config->MaxTxDs); + tmp_v_addr += + (config->TxCfg[i].FifoLen * (sizeof(TxD_t)) * + config->MaxTxDs); + } + + /* Allocation and initialization of RXDs in Rings */ + size = 0; + for (i = 0; i < config->RxRingNum; i++) { + if (config->RxCfg[i].NumRxd % (MAX_RXDS_PER_BLOCK + 1)) { + DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name); + DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", + i); + DBG_PRINT(ERR_DBG, "RxDs per Block"); + return FAILURE; + } + size += config->RxCfg[i].NumRxd; + nic->block_count[i] = + config->RxCfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1); + nic->pkt_cnt[i] = + config->RxCfg[i].NumRxd - nic->block_count[i]; + } + size = (size * (sizeof(RxD_t))); + mac_control->rxd_ring_mem_sz = size; + + for (i = 0; i < config->RxRingNum; i++) { + mac_control->rx_curr_get_info[i].block_index = 0; + mac_control->rx_curr_get_info[i].offset = 0; + mac_control->rx_curr_get_info[i].ring_len = + config->RxCfg[i].NumRxd - 1; + mac_control->rx_curr_put_info[i].block_index = 0; + mac_control->rx_curr_put_info[i].offset = 0; + mac_control->rx_curr_put_info[i].ring_len = + config->RxCfg[i].NumRxd - 1; + blk_cnt = + config->RxCfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1); + /* Allocating all the Rx blocks */ + for (j = 0; j < blk_cnt; j++) { + size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t)); + tmp_v_addr = pci_alloc_consistent(nic->pdev, size, + &tmp_p_addr); + if (tmp_v_addr == NULL) { + /* In case of failure, freeSharedMem() + * is called, which should free any + * memory that was alloced till the + * failure happened. + */ + nic->rx_blocks[i][j].block_virt_addr = + tmp_v_addr; + return -ENOMEM; + } + memset(tmp_v_addr, 0, size); + nic->rx_blocks[i][j].block_virt_addr = tmp_v_addr; + nic->rx_blocks[i][j].block_dma_addr = tmp_p_addr; + } + /* Interlinking all Rx Blocks */ + for (j = 0; j < blk_cnt; j++) { + tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr; + tmp_v_addr_next = + nic->rx_blocks[i][(j + 1) % + blk_cnt].block_virt_addr; + tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr; + tmp_p_addr_next = + nic->rx_blocks[i][(j + 1) % + blk_cnt].block_dma_addr; + + pre_rxd_blk = (RxD_block_t *) tmp_v_addr; + pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD + * marker. + */ + pre_rxd_blk->reserved_2_pNext_RxD_block = + (unsigned long) tmp_v_addr_next; + pre_rxd_blk->pNext_RxD_Blk_physical = + (u64) tmp_p_addr_next; + } + } + + /* Allocation and initialization of Statistics block */ + size = sizeof(StatInfo_t); + mac_control->stats_mem = pci_alloc_consistent + (nic->pdev, size, &mac_control->stats_mem_phy); + + if (!mac_control->stats_mem) { + /* In case of failure, freeSharedMem() is called, which + * should free any memory that was alloced till the + * failure happened. + */ + return -ENOMEM; + } + mac_control->stats_mem_sz = size; + + tmp_v_addr = mac_control->stats_mem; + mac_control->StatsInfo = (StatInfo_t *) tmp_v_addr; + memset(tmp_v_addr, 0, size); + + DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name, + (unsigned long long) tmp_p_addr); + + return SUCCESS; +} + +/* + * Input Arguments: + * Device peivate variable. + * Return Value: + * NONE + * Description: + * This function is to free all memory locations allocated by + * the initSharedMem() function and return it to the kernel. + */ +static void freeSharedMem(struct s2io_nic *nic) +{ + int i, j, blk_cnt, size; + void *tmp_v_addr; + dma_addr_t tmp_p_addr; + mac_info_t *mac_control; + struct config_param *config; + + + if (!nic) + return; + + mac_control = &nic->mac_control; + config = &nic->config; + + if (mac_control->txd_list_mem) { + pci_free_consistent(nic->pdev, + mac_control->txd_list_mem_sz, + mac_control->txd_list_mem, + mac_control->txd_list_mem_phy); + } + + size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t)); + for (i = 0; i < config->RxRingNum; i++) { + blk_cnt = nic->block_count[i]; + for (j = 0; j < blk_cnt; j++) { + tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr; + tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr; + if (tmp_v_addr == NULL) + break; + pci_free_consistent(nic->pdev, size, + tmp_v_addr, tmp_p_addr); + } + } + + if (mac_control->stats_mem) { + pci_free_consistent(nic->pdev, + mac_control->stats_mem_sz, + mac_control->stats_mem, + mac_control->stats_mem_phy); + } +} + +/* + * Input Arguments: + * device peivate variable + * Return Value: + * SUCCESS on success and '-1' on failure (endian settings incorrect). + * Description: + * The function sequentially configures every block + * of the H/W from their reset values. + */ +static int initNic(struct s2io_nic *nic) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + struct net_device *dev = nic->dev; + register u64 val64 = 0; + void *add; + u32 time; + int i, j; + mac_info_t *mac_control; + struct config_param *config; + int mdio_cnt = 0, dtx_cnt = 0; + unsigned long long print_var, mem_share; + + mac_control = &nic->mac_control; + config = &nic->config; + + /* Set proper endian settings and verify the same by + * reading the PIF Feed-back register. + */ +#ifdef __BIG_ENDIAN + /* The device by default set to a big endian format, so + * a big endian driver need not set anything. + */ + writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl); + val64 = (SWAPPER_CTRL_PIF_R_FE | + SWAPPER_CTRL_PIF_R_SE | + SWAPPER_CTRL_PIF_W_FE | + SWAPPER_CTRL_PIF_W_SE | + SWAPPER_CTRL_TXP_FE | + SWAPPER_CTRL_TXP_SE | + SWAPPER_CTRL_TXD_R_FE | + SWAPPER_CTRL_TXD_W_FE | + SWAPPER_CTRL_TXF_R_FE | + SWAPPER_CTRL_RXD_R_FE | + SWAPPER_CTRL_RXD_W_FE | + SWAPPER_CTRL_RXF_W_FE | + SWAPPER_CTRL_XMSI_FE | + SWAPPER_CTRL_XMSI_SE | + SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE); + writeq(val64, &bar0->swapper_ctrl); +#else + /* Initially we enable all bits to make it accessible by + * the driver, then we selectively enable only those bits + * that we want to set. + */ + writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl); + val64 = (SWAPPER_CTRL_PIF_R_FE | + SWAPPER_CTRL_PIF_R_SE | + SWAPPER_CTRL_PIF_W_FE | + SWAPPER_CTRL_PIF_W_SE | + SWAPPER_CTRL_TXP_FE | + SWAPPER_CTRL_TXP_SE | + SWAPPER_CTRL_TXD_R_FE | + SWAPPER_CTRL_TXD_R_SE | + SWAPPER_CTRL_TXD_W_FE | + SWAPPER_CTRL_TXD_W_SE | + SWAPPER_CTRL_TXF_R_FE | + SWAPPER_CTRL_RXD_R_FE | + SWAPPER_CTRL_RXD_R_SE | + SWAPPER_CTRL_RXD_W_FE | + SWAPPER_CTRL_RXD_W_SE | + SWAPPER_CTRL_RXF_W_FE | + SWAPPER_CTRL_XMSI_FE | + SWAPPER_CTRL_XMSI_SE | + SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE); + writeq(val64, &bar0->swapper_ctrl); +#endif + + /* Verifying if endian settings are accurate by reading + * a feedback register. + */ + val64 = readq(&bar0->pif_rd_swapper_fb); + if (val64 != 0x0123456789ABCDEFULL) { + /* Endian settings are incorrect, calls for another dekko. */ + print_var = (unsigned long long) val64; + DBG_PRINT(INIT_DBG, "%s: Endian settings are wrong", + dev->name); + DBG_PRINT(ERR_DBG, ", feedback read %llx\n", print_var); + + return FAILURE; + } + + /* Remove XGXS from reset state */ + val64 = 0; + writeq(val64, &bar0->sw_reset); + val64 = readq(&bar0->sw_reset); + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 2); + + /* Enable Receiving broadcasts */ + val64 = readq(&bar0->mac_cfg); + val64 |= MAC_RMAC_BCAST_ENABLE; + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writeq(val64, &bar0->mac_cfg); + + /* Read registers in all blocks */ + val64 = readq(&bar0->mac_int_mask); + val64 = readq(&bar0->mc_int_mask); + val64 = readq(&bar0->xgxs_int_mask); + + /* Set MTU */ + val64 = dev->mtu; + writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); + + /* Configuring the XAUI Interface of Xena. + ***************************************** + * To Configure the Xena's XAUI, one has to write a series + * of 64 bit values into two registers in a particular + * sequence. Hence a macro 'SWITCH_SIGN' has been defined + * which will be defined in the array of configuration values + * (default_dtx_cfg & default_mdio_cfg) at appropriate places + * to switch writing from one regsiter to another. We continue + * writing these values until we encounter the 'END_SIGN' macro. + * For example, After making a series of 21 writes into + * dtx_control register the 'SWITCH_SIGN' appears and hence we + * start writing into mdio_control until we encounter END_SIGN. + */ + while (1) { + dtx_cfg: + while (default_dtx_cfg[dtx_cnt] != END_SIGN) { + if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) { + dtx_cnt++; + goto mdio_cfg; + } + writeq(default_dtx_cfg[dtx_cnt], + &bar0->dtx_control); + val64 = readq(&bar0->dtx_control); + dtx_cnt++; + } + mdio_cfg: + while (default_mdio_cfg[mdio_cnt] != END_SIGN) { + if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) { + mdio_cnt++; + goto dtx_cfg; + } + writeq(default_mdio_cfg[mdio_cnt], + &bar0->mdio_control); + val64 = readq(&bar0->mdio_control); + mdio_cnt++; + } + if ((default_dtx_cfg[dtx_cnt] == END_SIGN) && + (default_mdio_cfg[mdio_cnt] == END_SIGN)) { + break; + } else { + goto dtx_cfg; + } + } + + /* Tx DMA Initialization */ + val64 = 0; + writeq(val64, &bar0->tx_fifo_partition_0); + writeq(val64, &bar0->tx_fifo_partition_1); + writeq(val64, &bar0->tx_fifo_partition_2); + writeq(val64, &bar0->tx_fifo_partition_3); + + + for (i = 0, j = 0; i < config->TxFIFONum; i++) { + val64 |= + vBIT(config->TxCfg[i].FifoLen - 1, ((i * 32) + 19), + 13) | vBIT(config->TxCfg[i].FifoPriority, + ((i * 32) + 5), 3); + + if (i == (config->TxFIFONum - 1)) { + if (i % 2 == 0) + i++; + } + + switch (i) { + case 1: + writeq(val64, &bar0->tx_fifo_partition_0); + val64 = 0; + break; + case 3: + writeq(val64, &bar0->tx_fifo_partition_1); + val64 = 0; + break; + case 5: + writeq(val64, &bar0->tx_fifo_partition_2); + val64 = 0; + break; + case 7: + writeq(val64, &bar0->tx_fifo_partition_3); + break; + } + } + + /* Enable Tx FIFO partition 0. */ + val64 = readq(&bar0->tx_fifo_partition_0); + val64 |= BIT(0); /* To enable the FIFO partition. */ + writeq(val64, &bar0->tx_fifo_partition_0); + + val64 = readq(&bar0->tx_fifo_partition_0); + DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n", + &bar0->tx_fifo_partition_0, (unsigned long long) val64); + + /* + * Initialization of Tx_PA_CONFIG register to ignore packet + * integrity checking. + */ + val64 = readq(&bar0->tx_pa_cfg); + val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI | + TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR; + writeq(val64, &bar0->tx_pa_cfg); + + /* Rx DMA intialization. */ + val64 = 0; + for (i = 0; i < config->RxRingNum; i++) { + val64 |= + vBIT(config->RxCfg[i].RingPriority, (5 + (i * 8)), 3); + } + writeq(val64, &bar0->rx_queue_priority); + + /* Allocating equal share of memory to all the configured + * Rings. + */ + val64 = 0; + for (i = 0; i < config->RxRingNum; i++) { + switch (i) { + case 0: + mem_share = (64 / config->RxRingNum + + 64 % config->RxRingNum); + val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); + continue; + case 1: + mem_share = (64 / config->RxRingNum); + val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); + continue; + case 2: + mem_share = (64 / config->RxRingNum); + val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); + continue; + case 3: + mem_share = (64 / config->RxRingNum); + val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); + continue; + case 4: + mem_share = (64 / config->RxRingNum); + val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); + continue; + case 5: + mem_share = (64 / config->RxRingNum); + val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); + continue; + case 6: + mem_share = (64 / config->RxRingNum); + val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); + continue; + case 7: + mem_share = (64 / config->RxRingNum); + val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); + continue; + } + } + writeq(val64, &bar0->rx_queue_cfg); + + /* Initializing the Tx round robin registers to 0. + * Filling Tx and Rx round robin registers as per the + * number of FIFOs and Rings is still TODO. + */ + writeq(0, &bar0->tx_w_round_robin_0); + writeq(0, &bar0->tx_w_round_robin_1); + writeq(0, &bar0->tx_w_round_robin_2); + writeq(0, &bar0->tx_w_round_robin_3); + writeq(0, &bar0->tx_w_round_robin_4); + + /* Disable Rx steering. Hard coding all packets be steered to + * Queue 0 for now. + * TODO*/ + if (rx_prio) { + u64 def = 0x8000000000000000ULL, tmp; + for (i = 0; i < MAX_RX_RINGS; i++) { + tmp = (u64) (def >> (i % config->RxRingNum)); + val64 |= (u64) (tmp >> (i * 8)); + } + writeq(val64, &bar0->rts_qos_steering); + } else { + val64 = 0x8080808080808080ULL; + writeq(val64, &bar0->rts_qos_steering); + } + + /* UDP Fix */ + val64 = 0; + for (i = 1; i < 8; i++) + writeq(val64, &bar0->rts_frm_len_n[i]); + + /* Set rts_frm_len register for fifo 0 */ + writeq(MAC_RTS_FRM_LEN_SET(dev->mtu + 22), + &bar0->rts_frm_len_n[0]); + + /* Enable statistics */ + writeq(mac_control->stats_mem_phy, &bar0->stat_addr); + val64 = SET_UPDT_PERIOD(8) | STAT_CFG_STAT_RO | STAT_CFG_STAT_EN; + writeq(val64, &bar0->stat_cfg); + + /* Initializing the sampling rate for the device to calculate the + * bandwidth utilization. + */ + val64 = MAC_TX_LINK_UTIL_VAL(0x5) | MAC_RX_LINK_UTIL_VAL(0x5); + writeq(val64, &bar0->mac_link_util); + + + /* Initializing the Transmit and Receive Traffic Interrupt + * Scheme. + */ + /* TTI Initialization */ + val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0xFFF) | + TTI_DATA1_MEM_TX_URNG_A(0xA) | TTI_DATA1_MEM_TX_URNG_B(0x10) | + TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN; + writeq(val64, &bar0->tti_data1_mem); + + val64 = + TTI_DATA2_MEM_TX_UFC_A(0x10) | TTI_DATA2_MEM_TX_UFC_B(0x20) | + TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80); + writeq(val64, &bar0->tti_data2_mem); + + val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; + writeq(val64, &bar0->tti_command_mem); + + /* Once the operation completes, the Strobe bit of the command + * register will be reset. We poll for this particular condition + * We wait for a maximum of 500ms for the operation to complete, + * if it's not complete by then we return error. + */ + time = 0; + while (TRUE) { + val64 = readq(&bar0->tti_command_mem); + if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { + break; + } + if (time > 10) { + DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n", + dev->name); + return -1; + } + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 20); + time++; + } + + /* RTI Initialization */ + val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF) | + RTI_DATA1_MEM_RX_URNG_A(0xA) | RTI_DATA1_MEM_RX_URNG_B(0x10) | + RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN; + writeq(val64, &bar0->rti_data1_mem); + + val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | RTI_DATA2_MEM_RX_UFC_B(0x2) | + RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80); + writeq(val64, &bar0->rti_data2_mem); + + val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD; + writeq(val64, &bar0->rti_command_mem); + + /* Once the operation completes, the Strobe bit of the command + * register will be reset. We poll for this particular condition + * We wait for a maximum of 500ms for the operation to complete, + * if it's not complete by then we return error. + */ + time = 0; + while (TRUE) { + val64 = readq(&bar0->rti_command_mem); + if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { + break; + } + if (time > 10) { + DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n", + dev->name); + return -1; + } + time++; + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 20); + } + + /* Initializing proper values as Pause threshold into all + * the 8 Queues on Rx side. + */ + writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); + writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); + + /* Disable RMAC PAD STRIPPING */ + add = (void *) &bar0->mac_cfg; + val64 = readq(&bar0->mac_cfg); + val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writel((u32) (val64), add); + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writel((u32) (val64 >> 32), (add + 4)); + val64 = readq(&bar0->mac_cfg); + + return SUCCESS; +} + +/* + * Input Arguments: + * device private variable, + * A mask indicating which Intr block must be modified and, + * A flag indicating whether to enable or disable the Intrs. + * Return Value: + * NONE. + * Description: + * This function will either disable or enable the interrupts + * depending on the flag argument. The mask argument can be used to + * enable/disable any Intr block. + */ +static void en_dis_able_NicIntrs(struct s2io_nic *nic, u16 mask, int flag) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + register u64 val64 = 0, temp64 = 0; + + /* Top level interrupt classification */ + /* PIC Interrupts */ + if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) { + /* Enable PIC Intrs in the general intr mask register */ + val64 = TXPIC_INT_M | PIC_RX_INT_M; + if (flag == ENABLE_INTRS) { + temp64 = readq(&bar0->general_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->general_int_mask); + /* Disabled all PCIX, Flash, MDIO, IIC and GPIO + * interrupts for now. + * TODO */ + writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); + /* No MSI Support is available presently, so TTI and + * RTI interrupts are also disabled. + */ + } else if (flag == DISABLE_INTRS) { + /* Disable PIC Intrs in the general intr mask register + */ + writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); + temp64 = readq(&bar0->general_int_mask); + val64 |= temp64; + writeq(val64, &bar0->general_int_mask); + } + } + + /* DMA Interrupts */ + /* Enabling/Disabling Tx DMA interrupts */ + if (mask & TX_DMA_INTR) { + /* Enable TxDMA Intrs in the general intr mask register */ + val64 = TXDMA_INT_M; + if (flag == ENABLE_INTRS) { + temp64 = readq(&bar0->general_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->general_int_mask); + /* Disable all interrupts other than PFC interrupt in + * DMA level. + */ + val64 = DISABLE_ALL_INTRS & (~TXDMA_PFC_INT_M); + writeq(val64, &bar0->txdma_int_mask); + /* Enable only the MISC error 1 interrupt in PFC block + */ + val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1); + writeq(val64, &bar0->pfc_err_mask); + } else if (flag == DISABLE_INTRS) { + /* Disable TxDMA Intrs in the general intr mask + * register */ + writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask); + writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask); + temp64 = readq(&bar0->general_int_mask); + val64 |= temp64; + writeq(val64, &bar0->general_int_mask); + } + } + + /* Enabling/Disabling Rx DMA interrupts */ + if (mask & RX_DMA_INTR) { + /* Enable RxDMA Intrs in the general intr mask register */ + val64 = RXDMA_INT_M; + if (flag == ENABLE_INTRS) { + temp64 = readq(&bar0->general_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->general_int_mask); + /* All RxDMA block interrupts are disabled for now + * TODO */ + writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); + } else if (flag == DISABLE_INTRS) { + /* Disable RxDMA Intrs in the general intr mask + * register */ + writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); + temp64 = readq(&bar0->general_int_mask); + val64 |= temp64; + writeq(val64, &bar0->general_int_mask); + } + } + + /* MAC Interrupts */ + /* Enabling/Disabling MAC interrupts */ + if (mask & (TX_MAC_INTR | RX_MAC_INTR)) { + val64 = TXMAC_INT_M | RXMAC_INT_M; + if (flag == ENABLE_INTRS) { + temp64 = readq(&bar0->general_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->general_int_mask); + /* All MAC block error interrupts are disabled for now + * except the link status change interrupt. + * TODO*/ + val64 = MAC_INT_STATUS_RMAC_INT; + temp64 = readq(&bar0->mac_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->mac_int_mask); + + val64 = readq(&bar0->mac_rmac_err_mask); + val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT); + writeq(val64, &bar0->mac_rmac_err_mask); + } else if (flag == DISABLE_INTRS) { + /* Disable MAC Intrs in the general intr mask register + */ + writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask); + writeq(DISABLE_ALL_INTRS, + &bar0->mac_rmac_err_mask); + + temp64 = readq(&bar0->general_int_mask); + val64 |= temp64; + writeq(val64, &bar0->general_int_mask); + } + } + + /* XGXS Interrupts */ + if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) { + val64 = TXXGXS_INT_M | RXXGXS_INT_M; + if (flag == ENABLE_INTRS) { + temp64 = readq(&bar0->general_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->general_int_mask); + /* All XGXS block error interrupts are disabled for now + * TODO */ + writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); + } else if (flag == DISABLE_INTRS) { + /* Disable MC Intrs in the general intr mask register + */ + writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); + temp64 = readq(&bar0->general_int_mask); + val64 |= temp64; + writeq(val64, &bar0->general_int_mask); + } + } + + /* Memory Controller(MC) interrupts */ + if (mask & MC_INTR) { + val64 = MC_INT_M; + if (flag == ENABLE_INTRS) { + temp64 = readq(&bar0->general_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->general_int_mask); + /* All MC block error interrupts are disabled for now + * TODO */ + writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask); + } else if (flag == DISABLE_INTRS) { + /* Disable MC Intrs in the general intr mask register + */ + writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask); + temp64 = readq(&bar0->general_int_mask); + val64 |= temp64; + writeq(val64, &bar0->general_int_mask); + } + } + + + /* Tx traffic interrupts */ + if (mask & TX_TRAFFIC_INTR) { + val64 = TXTRAFFIC_INT_M; + if (flag == ENABLE_INTRS) { + temp64 = readq(&bar0->general_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->general_int_mask); + /* Enable all the Tx side interrupts */ + writeq(0x0, &bar0->tx_traffic_mask); /* '0' Enables + * all 64 TX + * interrupt + * levels. + */ + } else if (flag == DISABLE_INTRS) { + /* Disable Tx Traffic Intrs in the general intr mask + * register. + */ + writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); + temp64 = readq(&bar0->general_int_mask); + val64 |= temp64; + writeq(val64, &bar0->general_int_mask); + } + } + + /* Rx traffic interrupts */ + if (mask & RX_TRAFFIC_INTR) { + val64 = RXTRAFFIC_INT_M; + if (flag == ENABLE_INTRS) { + temp64 = readq(&bar0->general_int_mask); + temp64 &= ~((u64) val64); + writeq(temp64, &bar0->general_int_mask); + writeq(0x0, &bar0->rx_traffic_mask); /* '0' Enables + * all 8 RX + * interrupt + * levels. + */ + } else if (flag == DISABLE_INTRS) { + /* Disable Rx Traffic Intrs in the general intr mask + * register. + */ + writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); + temp64 = readq(&bar0->general_int_mask); + val64 |= temp64; + writeq(val64, &bar0->general_int_mask); + } + } +} + +/* + * Input Arguments: + * val64 - Value read from adapter status register. + * flag - indicates if the adapter enable bit was ever written once before. + * Return Value: + * void. + * Description: + * Returns whether the H/W is ready to go or not. Depending on whether + * adapter enable bit was written or not the comparison differs and the + * calling function passes the input argument flag to indicate this. + */ +static int verify_xena_quiescence(u64 val64, int flag) +{ + int ret = 0; + u64 tmp64 = ~((u64) val64); + + if (! + (tmp64 & + (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY | + ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY | + ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | + ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | + ADAPTER_STATUS_P_PLL_LOCK))) { + if (flag == FALSE) { + if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) && + ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == + ADAPTER_STATUS_RC_PRC_QUIESCENT)) { + + ret = 1; + + } + } else { + if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == + ADAPTER_STATUS_RMAC_PCC_IDLE) && + (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || + ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == + ADAPTER_STATUS_RC_PRC_QUIESCENT))) { + + ret = 1; + + } + } + } + + return ret; +} + +/* + * New procedure to clear mac address reading problems on Alpha platforms + * + */ +void FixMacAddress(nic_t * sp) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u64 val64; + int i = 0; + + while (fix_mac[i] != END_SIGN) { + writeq(fix_mac[i++], &bar0->gpio_control); + val64 = readq(&bar0->gpio_control); + } +} + +/* + * Input Arguments: + * device private variable. + * Return Value: + * SUCCESS on success and -1 on failure. + * Description: + * This function actually turns the device on. Before this + * function is called, all Registers are configured from their reset states + * and shared memory is allocated but the NIC is still quiescent. On + * calling this function, the device interrupts are cleared and the NIC is + * literally switched on by writing into the adapter control register. + */ +static int startNic(struct s2io_nic *nic) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + struct net_device *dev = nic->dev; + register u64 val64 = 0; + u16 interruptible, i; + u16 subid; + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &nic->mac_control; + config = &nic->config; + + /* PRC Initialization and configuration */ + for (i = 0; i < config->RxRingNum; i++) { + writeq((u64) nic->rx_blocks[i][0].block_dma_addr, + &bar0->prc_rxd0_n[i]); + + val64 = readq(&bar0->prc_ctrl_n[i]); + val64 |= PRC_CTRL_RC_ENABLED; + writeq(val64, &bar0->prc_ctrl_n[i]); + } + + /* Enabling MC-RLDRAM. After enabling the device, we timeout + * for around 100ms, which is approximately the time required + * for the device to be ready for operation. + */ + val64 = readq(&bar0->mc_rldram_mrs); + val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE; + writeq(val64, &bar0->mc_rldram_mrs); + val64 = readq(&bar0->mc_rldram_mrs); + + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 10); /* Delay by around 100 ms. */ + + /* Enabling ECC Protection. */ + val64 = readq(&bar0->adapter_control); + val64 &= ~ADAPTER_ECC_EN; + writeq(val64, &bar0->adapter_control); + + /* Clearing any possible Link state change interrupts that + * could have popped up just before Enabling the card. + */ + val64 = readq(&bar0->mac_rmac_err_reg); + if (val64) + writeq(val64, &bar0->mac_rmac_err_reg); + + /* Verify if the device is ready to be enabled, if so enable + * it. + */ + val64 = readq(&bar0->adapter_status); + if (!verify_xena_quiescence(val64, nic->device_enabled_once)) { + DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name); + DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n", + (unsigned long long) val64); + return FAILURE; + } + + /* Enable select interrupts */ + interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR | + RX_MAC_INTR; + en_dis_able_NicIntrs(nic, interruptible, ENABLE_INTRS); + + /* With some switches, link might be already up at this point. + * Because of this weird behavior, when we enable laser, + * we may not get link. We need to handle this. We cannot + * figure out which switch is misbehaving. So we are forced to + * make a global change. + */ + + /* Enabling Laser. */ + val64 = readq(&bar0->adapter_control); + val64 |= ADAPTER_EOI_TX_ON; + writeq(val64, &bar0->adapter_control); + + /* SXE-002: Initialize link and activity LED */ + subid = nic->pdev->subsystem_device; + if ((subid & 0xFF) >= 0x07) { + val64 = readq(&bar0->gpio_control); + val64 |= 0x0000800000000000ULL; + writeq(val64, &bar0->gpio_control); + val64 = 0x0411040400000000ULL; + writeq(val64, (void *) ((u8 *) bar0 + 0x2700)); + } + + /* + * Here we are performing soft reset on XGXS to + * force link down. Since link is already up, we will get + * link state change interrupt after this reset + */ + writeq(0x8007051500000000ULL, &bar0->dtx_control); + val64 = readq(&bar0->dtx_control); + writeq(0x80070515000000E0ULL, &bar0->dtx_control); + val64 = readq(&bar0->dtx_control); + writeq(0x80070515001F00E4ULL, &bar0->dtx_control); + val64 = readq(&bar0->dtx_control); + + return SUCCESS; +} + +/* + * Input Arguments: + * nic - device private variable. + * Return Value: + * void. + * Description: + * Free all queued Tx buffers. + */ +void freeTxBuffers(struct s2io_nic *nic) +{ + struct net_device *dev = nic->dev; + struct sk_buff *skb; + TxD_t *txdp; + int i, j; +#if DEBUG_ON + int cnt = 0; +#endif + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &nic->mac_control; + config = &nic->config; + + for (i = 0; i < config->TxFIFONum; i++) { + for (j = 0; j < config->TxCfg[i].FifoLen - 1; j++) { + txdp = mac_control->txdl_start[i] + + (config->MaxTxDs * j); + + if (!(txdp->Control_1 & TXD_LIST_OWN_XENA)) { + /* If owned by host, ignore */ + continue; + } + skb = + (struct sk_buff *) ((unsigned long) txdp-> + Host_Control); + if (skb == NULL) { + DBG_PRINT(ERR_DBG, "%s: NULL skb ", + dev->name); + DBG_PRINT(ERR_DBG, "in Tx Int\n"); + return; + } +#if DEBUG_ON + cnt++; +#endif + dev_kfree_skb(skb); + memset(txdp, 0, sizeof(TxD_t)); + } +#if DEBUG_ON + DBG_PRINT(INTR_DBG, + "%s:forcibly freeing %d skbs on FIFO%d\n", + dev->name, cnt, i); +#endif + } +} + +/* + * Input Arguments: + * nic - device private variable. + * Return Value: + * void. + * Description: + * This function does exactly the opposite of what the startNic() + * function does. This function is called to stop + * the device. + */ +static void stopNic(struct s2io_nic *nic) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + register u64 val64 = 0; + u16 interruptible, i; + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &nic->mac_control; + config = &nic->config; + +/* Disable all interrupts */ + interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR | + RX_MAC_INTR; + en_dis_able_NicIntrs(nic, interruptible, DISABLE_INTRS); + +/* Disable PRCs */ + for (i = 0; i < config->RxRingNum; i++) { + val64 = readq(&bar0->prc_ctrl_n[i]); + val64 &= ~((u64) PRC_CTRL_RC_ENABLED); + writeq(val64, &bar0->prc_ctrl_n[i]); + } +} + +/* + * Input Arguments: + * device private variable + * Return Value: + * SUCCESS on success or an appropriate -ve value on failure. + * Description: + * The function allocates Rx side skbs and puts the physical + * address of these buffers into the RxD buffer pointers, so that the NIC + * can DMA the received frame into these locations. + * The NIC supports 3 receive modes, viz + * 1. single buffer, + * 2. three buffer and + * 3. Five buffer modes. + * Each mode defines how many fragments the received frame will be split + * up into by the NIC. The frame is split into L3 header, L4 Header, + * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself + * is split into 3 fragments. As of now only single buffer mode is supported. + */ +int fill_rx_buffers(struct s2io_nic *nic, int ring_no) +{ + struct net_device *dev = nic->dev; + struct sk_buff *skb; + RxD_t *rxdp; + int off, off1, size, block_no, block_no1; + int offset, offset1; + u32 alloc_tab = 0; + u32 alloc_cnt = nic->pkt_cnt[ring_no] - + atomic_read(&nic->rx_bufs_left[ring_no]); + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &nic->mac_control; + config = &nic->config; + + if (frame_len[ring_no]) { + if (frame_len[ring_no] > dev->mtu) + dev->mtu = frame_len[ring_no]; + size = frame_len[ring_no] + HEADER_ETHERNET_II_802_3_SIZE + + HEADER_802_2_SIZE + HEADER_SNAP_SIZE; + } else { + size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + + HEADER_802_2_SIZE + HEADER_SNAP_SIZE; + } + + while (alloc_tab < alloc_cnt) { + block_no = mac_control->rx_curr_put_info[ring_no]. + block_index; + block_no1 = mac_control->rx_curr_get_info[ring_no]. + block_index; + off = mac_control->rx_curr_put_info[ring_no].offset; + off1 = mac_control->rx_curr_get_info[ring_no].offset; + offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off; + offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1; + + rxdp = nic->rx_blocks[ring_no][block_no]. + block_virt_addr + off; + if ((offset == offset1) && (rxdp->Host_Control)) { + DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name); + DBG_PRINT(INTR_DBG, " info equated\n"); + goto end; + } + + if (rxdp->Control_1 == END_OF_BLOCK) { + mac_control->rx_curr_put_info[ring_no]. + block_index++; + mac_control->rx_curr_put_info[ring_no]. + block_index %= nic->block_count[ring_no]; + block_no = mac_control->rx_curr_put_info + [ring_no].block_index; + off++; + off %= (MAX_RXDS_PER_BLOCK + 1); + mac_control->rx_curr_put_info[ring_no].offset = + off; + /*rxdp = nic->rx_blocks[ring_no][block_no]. + block_virt_addr + off; */ + rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2); + DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n", + dev->name, rxdp); + } + + if (rxdp->Control_1 & RXD_OWN_XENA) { + mac_control->rx_curr_put_info[ring_no]. + offset = off; + goto end; + } + + skb = dev_alloc_skb(size + HEADER_ALIGN_LAYER_3); + if (!skb) { + DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name); + DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n"); + return -ENOMEM; + } + skb_reserve(skb, HEADER_ALIGN_LAYER_3); + memset(rxdp, 0, sizeof(RxD_t)); + rxdp->Buffer0_ptr = pci_map_single + (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE); + rxdp->Control_2 &= (~MASK_BUFFER0_SIZE); + rxdp->Control_2 |= SET_BUFFER0_SIZE(size); + rxdp->Host_Control = (unsigned long) (skb); + rxdp->Control_1 |= RXD_OWN_XENA; + off++; + off %= (MAX_RXDS_PER_BLOCK + 1); + mac_control->rx_curr_put_info[ring_no].offset = off; + atomic_inc(&nic->rx_bufs_left[ring_no]); + alloc_tab++; + } + + end: + return SUCCESS; +} + +/* + * Input Arguments: + * device private variable. + * Return Value: + * NONE. + * Description: + * This function will free all Rx buffers allocated by host. + */ +static void freeRxBuffers(struct s2io_nic *sp) +{ + struct net_device *dev = sp->dev; + int i, j, blk = 0, off, buf_cnt = 0; + RxD_t *rxdp; + struct sk_buff *skb; + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &sp->mac_control; + config = &sp->config; + + for (i = 0; i < config->RxRingNum; i++) { + for (j = 0, blk = 0; j < config->RxCfg[i].NumRxd; j++) { + off = j % (MAX_RXDS_PER_BLOCK + 1); + rxdp = sp->rx_blocks[i][blk].block_virt_addr + off; + + if (rxdp->Control_1 == END_OF_BLOCK) { + rxdp = + (RxD_t *) ((unsigned long) rxdp-> + Control_2); + j++; + blk++; + } + + skb = + (struct sk_buff *) ((unsigned long) rxdp-> + Host_Control); + if (skb) { + pci_unmap_single(sp->pdev, (dma_addr_t) + rxdp->Buffer0_ptr, + dev->mtu + + HEADER_ETHERNET_II_802_3_SIZE + + HEADER_802_2_SIZE + + HEADER_SNAP_SIZE, + PCI_DMA_FROMDEVICE); + dev_kfree_skb(skb); + atomic_dec(&sp->rx_bufs_left[i]); + buf_cnt++; + } + memset(rxdp, 0, sizeof(RxD_t)); + } + mac_control->rx_curr_put_info[i].block_index = 0; + mac_control->rx_curr_get_info[i].block_index = 0; + mac_control->rx_curr_put_info[i].offset = 0; + mac_control->rx_curr_get_info[i].offset = 0; + atomic_set(&sp->rx_bufs_left[i], 0); + DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n", + dev->name, buf_cnt, i); + } +} + +/* + * Input Argument: + * dev - pointer to the device structure. + * budget - The number of packets that were budgeted to be processed during + * one pass through the 'Poll" function. + * Return value: + * 0 on success and 1 if there are No Rx packets to be processed. + * Description: + * Comes into picture only if NAPI support has been incorporated. It does + * the same thing that rxIntrHandler does, but not in a interrupt context + * also It will process only a given number of packets. + */ +#ifdef CONFIG_S2IO_NAPI +static int s2io_poll(struct net_device *dev, int *budget) +{ + nic_t *nic = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + int pkts_to_process = *budget, pkt_cnt = 0; + register u64 val64 = 0; + rx_curr_get_info_t offset_info; + int i, block_no; + u16 val16, cksum; + struct sk_buff *skb; + RxD_t *rxdp; + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &nic->mac_control; + config = &nic->config; + + if (pkts_to_process > dev->quota) + pkts_to_process = dev->quota; + + val64 = readq(&bar0->rx_traffic_int); + writeq(val64, &bar0->rx_traffic_int); + + for (i = 0; i < config->RxRingNum; i++) { + if (--pkts_to_process < 0) { + goto no_rx; + } + offset_info = mac_control->rx_curr_get_info[i]; + block_no = offset_info.block_index; + rxdp = nic->rx_blocks[i][block_no].block_virt_addr + + offset_info.offset; + while (!(rxdp->Control_1 & RXD_OWN_XENA)) { + if (rxdp->Control_1 == END_OF_BLOCK) { + rxdp = + (RxD_t *) ((unsigned long) rxdp-> + Control_2); + offset_info.offset++; + offset_info.offset %= + (MAX_RXDS_PER_BLOCK + 1); + block_no++; + block_no %= nic->block_count[i]; + mac_control->rx_curr_get_info[i]. + offset = offset_info.offset; + mac_control->rx_curr_get_info[i]. + block_index = block_no; + continue; + } + skb = + (struct sk_buff *) ((unsigned long) rxdp-> + Host_Control); + if (skb == NULL) { + DBG_PRINT(ERR_DBG, "%s: The skb is ", + dev->name); + DBG_PRINT(ERR_DBG, "Null in Rx Intr\n"); + return 0; + } + val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2); + val16 = (u16) (val64 >> 48); + cksum = RXD_GET_L4_CKSUM(rxdp->Control_1); + pci_unmap_single(nic->pdev, (dma_addr_t) + rxdp->Buffer0_ptr, + dev->mtu + + HEADER_ETHERNET_II_802_3_SIZE + + HEADER_802_2_SIZE + + HEADER_SNAP_SIZE, + PCI_DMA_FROMDEVICE); + rxOsmHandler(nic, val16, rxdp, i); + pkt_cnt++; + offset_info.offset++; + offset_info.offset %= (MAX_RXDS_PER_BLOCK + 1); + rxdp = + nic->rx_blocks[i][block_no].block_virt_addr + + offset_info.offset; + mac_control->rx_curr_get_info[i].offset = + offset_info.offset; + } + } + if (!pkt_cnt) + pkt_cnt = 1; + + for (i = 0; i < config->RxRingNum; i++) + fill_rx_buffers(nic, i); + + dev->quota -= pkt_cnt; + *budget -= pkt_cnt; + netif_rx_complete(dev); + +/* Re enable the Rx interrupts. */ + en_dis_able_NicIntrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS); + return 0; + + no_rx: + for (i = 0; i < config->RxRingNum; i++) + fill_rx_buffers(nic, i); + dev->quota -= pkt_cnt; + *budget -= pkt_cnt; + return 1; +} +#else +/* + * Input Arguments: + * device private variable. + * Return Value: + * NONE. + * Description: + * If the interrupt is because of a received frame or if the + * receive ring contains fresh as yet un-processed frames, this function is + * called. It picks out the RxD at which place the last Rx processing had + * stopped and sends the skb to the OSM's Rx handler and then increments + * the offset. + */ +static void rxIntrHandler(struct s2io_nic *nic) +{ + struct net_device *dev = (struct net_device *) nic->dev; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + rx_curr_get_info_t offset_info; + RxD_t *rxdp; + struct sk_buff *skb; + u16 val16, cksum; + register u64 val64 = 0; + int i, block_no; + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &nic->mac_control; + config = &nic->config; + +#if DEBUG_ON + nic->rxint_cnt++; +#endif + +/* rx_traffic_int reg is an R1 register, hence we read and write back + * the samevalue in the register to clear it. + */ + val64 = readq(&bar0->rx_traffic_int); + writeq(val64, &bar0->rx_traffic_int); + + for (i = 0; i < config->RxRingNum; i++) { + offset_info = mac_control->rx_curr_get_info[i]; + block_no = offset_info.block_index; + rxdp = nic->rx_blocks[i][block_no].block_virt_addr + + offset_info.offset; + while (!(rxdp->Control_1 & RXD_OWN_XENA)) { + if (rxdp->Control_1 == END_OF_BLOCK) { + rxdp = (RxD_t *) ((unsigned long) + rxdp->Control_2); + offset_info.offset++; + offset_info.offset %= + (MAX_RXDS_PER_BLOCK + 1); + block_no++; + block_no %= nic->block_count[i]; + mac_control->rx_curr_get_info[i]. + offset = offset_info.offset; + mac_control->rx_curr_get_info[i]. + block_index = block_no; + continue; + } + skb = (struct sk_buff *) ((unsigned long) + rxdp->Host_Control); + if (skb == NULL) { + DBG_PRINT(ERR_DBG, "%s: The skb is ", + dev->name); + DBG_PRINT(ERR_DBG, "Null in Rx Intr\n"); + return; + } + val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2); + val16 = (u16) (val64 >> 48); + cksum = RXD_GET_L4_CKSUM(rxdp->Control_1); + pci_unmap_single(nic->pdev, (dma_addr_t) + rxdp->Buffer0_ptr, + dev->mtu + + HEADER_ETHERNET_II_802_3_SIZE + + HEADER_802_2_SIZE + + HEADER_SNAP_SIZE, + PCI_DMA_FROMDEVICE); + rxOsmHandler(nic, val16, rxdp, i); + offset_info.offset++; + offset_info.offset %= (MAX_RXDS_PER_BLOCK + 1); + rxdp = + nic->rx_blocks[i][block_no].block_virt_addr + + offset_info.offset; + mac_control->rx_curr_get_info[i].offset = + offset_info.offset; + } + } +} +#endif + +/* + * Input Arguments: + * device private variable + * Return Value: + * NONE + * Description: + * If an interrupt was raised to indicate DMA complete of the + * Tx packet, this function is called. It identifies the last TxD whose buffer + * was freed and frees all skbs whose data have already DMA'ed into the NICs + * internal memory. + */ +static void txIntrHandler(struct s2io_nic *nic) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + struct net_device *dev = (struct net_device *) nic->dev; + tx_curr_get_info_t offset_info, offset_info1; + struct sk_buff *skb; + TxD_t *txdlp; + register u64 val64 = 0; + int i; + u16 j, frg_cnt; + mac_info_t *mac_control; + struct config_param *config; +#if DEBUG_ON + int cnt = 0; + nic->txint_cnt++; +#endif + + mac_control = &nic->mac_control; + config = &nic->config; + + /* tx_traffic_int reg is an R1 register, hence we read and write + * back the samevalue in the register to clear it. + */ + val64 = readq(&bar0->tx_traffic_int); + writeq(val64, &bar0->tx_traffic_int); + + for (i = 0; i < config->TxFIFONum; i++) { + offset_info = mac_control->tx_curr_get_info[i]; + offset_info1 = mac_control->tx_curr_put_info[i]; + txdlp = mac_control->txdl_start[i] + + (config->MaxTxDs * offset_info.offset); + while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && + (offset_info.offset != offset_info1.offset) && + (txdlp->Host_Control)) { + /* Check for TxD errors */ + if (txdlp->Control_1 & TXD_T_CODE) { + unsigned long long err; + err = txdlp->Control_1 & TXD_T_CODE; + DBG_PRINT(ERR_DBG, "***TxD error %llx\n", + err); + } + + skb = (struct sk_buff *) ((unsigned long) + txdlp->Host_Control); + if (skb == NULL) { + DBG_PRINT(ERR_DBG, "%s: Null skb ", + dev->name); + DBG_PRINT(ERR_DBG, "in Tx Free Intr\n"); + return; + } + nic->tx_pkt_count++; + + frg_cnt = skb_shinfo(skb)->nr_frags; + + /* For unfragmented skb */ + pci_unmap_single(nic->pdev, (dma_addr_t) + txdlp->Buffer_Pointer, + skb->len - skb->data_len, + PCI_DMA_TODEVICE); + if (frg_cnt) { + TxD_t *temp = txdlp; + txdlp++; + for (j = 0; j < frg_cnt; j++, txdlp++) { + skb_frag_t *frag = + &skb_shinfo(skb)->frags[j]; + pci_unmap_page(nic->pdev, + (dma_addr_t) + txdlp-> + Buffer_Pointer, + frag->size, + PCI_DMA_TODEVICE); + } + txdlp = temp; + } + memset(txdlp, 0, + (sizeof(TxD_t) * config->MaxTxDs)); + + /* Updating the statistics block */ + nic->stats.tx_packets++; + nic->stats.tx_bytes += skb->len; +#if DEBUG_ON + nic->txpkt_bytes += skb->len; + cnt++; +#endif + dev_kfree_skb_irq(skb); + + offset_info.offset++; + offset_info.offset %= offset_info.fifo_len + 1; + txdlp = mac_control->txdl_start[i] + + (config->MaxTxDs * offset_info.offset); + mac_control->tx_curr_get_info[i].offset = + offset_info.offset; + } +#if DEBUG_ON + DBG_PRINT(INTR_DBG, "%s: freed %d Tx Pkts\n", dev->name, + cnt); +#endif + } + + spin_lock(&nic->tx_lock); + if (netif_queue_stopped(dev)) + netif_wake_queue(dev); + spin_unlock(&nic->tx_lock); +} + +/* + * Input Arguments: + * device private variable + * Return Value: + * NONE + * Description: + * If the interrupt was neither because of Rx packet or Tx + * complete, this function is called. If the interrupt was to indicate a loss + * of link, the OSM link status handler is invoked for any other alarm + * interrupt the block that raised the interrupt is displayed and a H/W reset + * is issued. + */ +static void alarmIntrHandler(struct s2io_nic *nic) +{ + struct net_device *dev = (struct net_device *) nic->dev; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + register u64 val64 = 0, err_reg = 0; + + + /* Handling link status change error Intr */ + err_reg = readq(&bar0->mac_rmac_err_reg); + if (err_reg & RMAC_LINK_STATE_CHANGE_INT) { + schedule_work(&nic->set_link_task); + } + + /* Handling SERR errors by stopping device Xmit queue and forcing + * a H/W reset. + */ + val64 = readq(&bar0->serr_source); + if (val64 & SERR_SOURCE_ANY) { + DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name); + DBG_PRINT(ERR_DBG, "serious error!!\n"); + netif_stop_queue(dev); + } +/* Other type of interrupts are not being handled now, TODO*/ +} + +/* + * Input Argument: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * Return value: + * SUCCESS on success and FAILURE on failure. + * Description: + * Function that waits for a command to Write into RMAC ADDR DATA registers + * to be completed and returns either success or error depending on whether + * the command was complete or not. + */ +int waitForCmdComplete(nic_t * sp) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + int ret = FAILURE, cnt = 0; + u64 val64; + + while (TRUE) { + val64 = + RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD + | RMAC_ADDR_CMD_MEM_OFFSET(0); + writeq(val64, &bar0->rmac_addr_cmd_mem); + val64 = readq(&bar0->rmac_addr_cmd_mem); + if (!val64) { + ret = SUCCESS; + break; + } + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 20); + if (cnt++ > 10) + break; + } + + return ret; +} + +/* + * Input Argument: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * Return value: + * void. + * Description: + * Function to Reset the card. This function then also restores the previously + * saved PCI configuration space registers as the card reset also resets the + * Configration space. + */ +void s2io_reset(nic_t * sp) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u64 val64; + u16 subid; + + val64 = SW_RESET_ALL; + writeq(val64, &bar0->sw_reset); + + /* At this stage, if the PCI write is indeed completed, the + * card is reset and so is the PCI Config space of the device. + * So a read cannot be issued at this stage on any of the + * registers to ensure the write into "sw_reset" register + * has gone through. + * Question: Is there any system call that will explicitly force + * all the write commands still pending on the bus to be pushed + * through? + * As of now I'am just giving a 250ms delay and hoping that the + * PCI write to sw_reset register is done by this time. + */ + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 4); + + /* Restore the PCI state saved during initializarion. */ + pci_restore_state(sp->pdev, sp->config_space); + s2io_init_pci(sp); + + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 4); + + /* SXE-002: Configure link and activity LED to turn it off */ + subid = sp->pdev->subsystem_device; + if ((subid & 0xFF) >= 0x07) { + val64 = readq(&bar0->gpio_control); + val64 |= 0x0000800000000000ULL; + writeq(val64, &bar0->gpio_control); + val64 = 0x0411040400000000ULL; + writeq(val64, (void *) ((u8 *) bar0 + 0x2700)); + } + + sp->device_enabled_once = FALSE; +} + +/* + * Input Argument: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * Return value: + * SUCCESS on success and FAILURE on failure. + * Description: + * Function to set the swapper control on the card correctly depending on the + * 'endianness' of the system. + */ +int s2io_set_swapper(nic_t * sp) +{ + struct net_device *dev = sp->dev; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u64 val64; + +/* Set proper endian settings and verify the same by reading the PIF + * Feed-back register. + */ +#ifdef __BIG_ENDIAN +/* The device by default set to a big endian format, so a big endian + * driver need not set anything. + */ + writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl); + val64 = (SWAPPER_CTRL_PIF_R_FE | + SWAPPER_CTRL_PIF_R_SE | + SWAPPER_CTRL_PIF_W_FE | + SWAPPER_CTRL_PIF_W_SE | + SWAPPER_CTRL_TXP_FE | + SWAPPER_CTRL_TXP_SE | + SWAPPER_CTRL_TXD_R_FE | + SWAPPER_CTRL_TXD_W_FE | + SWAPPER_CTRL_TXF_R_FE | + SWAPPER_CTRL_RXD_R_FE | + SWAPPER_CTRL_RXD_W_FE | + SWAPPER_CTRL_RXF_W_FE | + SWAPPER_CTRL_XMSI_FE | + SWAPPER_CTRL_XMSI_SE | + SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE); + writeq(val64, &bar0->swapper_ctrl); +#else +/* Initially we enable all bits to make it accessible by the driver, + * then we selectively enable only those bits that we want to set. + */ + writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl); + val64 = (SWAPPER_CTRL_PIF_R_FE | + SWAPPER_CTRL_PIF_R_SE | + SWAPPER_CTRL_PIF_W_FE | + SWAPPER_CTRL_PIF_W_SE | + SWAPPER_CTRL_TXP_FE | + SWAPPER_CTRL_TXP_SE | + SWAPPER_CTRL_TXD_R_FE | + SWAPPER_CTRL_TXD_R_SE | + SWAPPER_CTRL_TXD_W_FE | + SWAPPER_CTRL_TXD_W_SE | + SWAPPER_CTRL_TXF_R_FE | + SWAPPER_CTRL_RXD_R_FE | + SWAPPER_CTRL_RXD_R_SE | + SWAPPER_CTRL_RXD_W_FE | + SWAPPER_CTRL_RXD_W_SE | + SWAPPER_CTRL_RXF_W_FE | + SWAPPER_CTRL_XMSI_FE | + SWAPPER_CTRL_XMSI_SE | + SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE); + writeq(val64, &bar0->swapper_ctrl); +#endif + +/* Verifying if endian settings are accurate by reading a feedback + * register. + */ + val64 = readq(&bar0->pif_rd_swapper_fb); + if (val64 != 0x0123456789ABCDEFULL) { + /* Endian settings are incorrect, calls for another dekko. */ + DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ", + dev->name); + DBG_PRINT(ERR_DBG, "feedback read %llx\n", + (unsigned long long) val64); + return FAILURE; + } + + return SUCCESS; +} + +/* ********************************************************* * + * Functions defined below concern the OS part of the driver * + * ********************************************************* */ + +/* + * Input Argument: + * dev - pointer to the device structure. + * Return value: + * '0' on success and an appropriate (-)ve integer as defined in errno.h + * file on failure. + * Description: + * This function is the open entry point of the driver. It mainly calls a + * function to allocate Rx buffers and inserts them into the buffer + * descriptors and then enables the Rx part of the NIC. + */ +int s2io_open(struct net_device *dev) +{ + nic_t *sp = dev->priv; + int i, ret = 0, err = 0; + mac_info_t *mac_control; + struct config_param *config; + + +/* Make sure you have link off by default every time Nic is initialized*/ + netif_carrier_off(dev); + sp->last_link_state = LINK_DOWN; + +/* Initialize the H/W I/O registers */ + if (initNic(sp) != 0) { + DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", + dev->name); + return -ENODEV; + } + +/* After proper initialization of H/W, register ISR */ + err = + request_irq((int) sp->irq, s2io_isr, SA_SHIRQ, sp->name, dev); + if (err) { + s2io_reset(sp); + DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n", + dev->name); + return err; + } + if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) { + DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n"); + s2io_reset(sp); + return -ENODEV; + } + + +/* Setting its receive mode */ + s2io_set_multicast(dev); + +/* Initializing the Rx buffers. For now we are considering only 1 Rx ring + * and initializing buffers into 1016 RxDs or 8 Rx blocks + */ + mac_control = &sp->mac_control; + config = &sp->config; + + for (i = 0; i < config->RxRingNum; i++) { + if ((ret = fill_rx_buffers(sp, i))) { + DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n", + dev->name); + s2io_reset(sp); + free_irq(dev->irq, dev); + freeRxBuffers(sp); + return -ENOMEM; + } + DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i, + atomic_read(&sp->rx_bufs_left[i])); + } + +/* Enable tasklet for the device */ + tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev); + +/* Enable Rx Traffic and interrupts on the NIC */ + if (startNic(sp)) { + DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name); + tasklet_kill(&sp->task); + s2io_reset(sp); + free_irq(dev->irq, dev); + freeRxBuffers(sp); + return -ENODEV; + } + + sp->device_close_flag = FALSE; /* Device is up and running. */ + netif_start_queue(dev); + + return 0; +} + +/* + * Input Argument/s: + * dev - device pointer. + * Return value: + * '0' on success and an appropriate (-)ve integer as defined in errno.h + * file on failure. + * Description: + * This is the stop entry point of the driver. It needs to undo exactly + * whatever was done by the open entry point, thus it's usually referred to + * as the close function. Among other things this function mainly stops the + * Rx side of the NIC and frees all the Rx buffers in the Rx rings. + */ +int s2io_close(struct net_device *dev) +{ + nic_t *sp = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + register u64 val64 = 0; + u16 cnt = 0; + + spin_lock(&sp->isr_lock); + netif_stop_queue(dev); + +/* disable Tx and Rx traffic on the NIC */ + stopNic(sp); + + spin_unlock(&sp->isr_lock); + +/* If the device tasklet is running, wait till its done before killing it */ + while (atomic_read(&(sp->tasklet_status))) { + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 10); + } + tasklet_kill(&sp->task); + +/* Check if the device is Quiescent and then Reset the NIC */ + do { + val64 = readq(&bar0->adapter_status); + if (verify_xena_quiescence(val64, sp->device_enabled_once)) { + break; + } + + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 20); + cnt++; + if (cnt == 10) { + DBG_PRINT(ERR_DBG, + "s2io_close:Device not Quiescent "); + DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n", + (unsigned long long) val64); + break; + } + } while (1); + s2io_reset(sp); + +/* Free the Registered IRQ */ + free_irq(dev->irq, dev); + +/* Free all Tx Buffers waiting for transmission */ + freeTxBuffers(sp); + +/* Free all Rx buffers allocated by host */ + freeRxBuffers(sp); + + sp->device_close_flag = TRUE; /* Device is shut down. */ + + return 0; +} + +/* + * Input Argument/s: + * skb - the socket buffer containing the Tx data. + * dev - device pointer. + * Return value: + * '0' on success & 1 on failure. + * NOTE: when device cant queue the pkt, just the trans_start variable will + * not be upadted. + * Description: + * This function is the Tx entry point of the driver. S2IO NIC supports + * certain protocol assist features on Tx side, namely CSO, S/G, LSO. + */ +int s2io_xmit(struct sk_buff *skb, struct net_device *dev) +{ + nic_t *sp = dev->priv; + u16 off, txd_len, frg_cnt, frg_len, i, queue, off1, queue_len; + register u64 val64; + TxD_t *txdp; + TxFIFO_element_t *tx_fifo; + unsigned long flags; +#ifdef NETIF_F_TSO + int mss; +#endif + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &sp->mac_control; + config = &sp->config; + + DBG_PRINT(TX_DBG, "%s: In S2IO Tx routine\n", dev->name); + + spin_lock_irqsave(&sp->tx_lock, flags); + queue = 0; + /* Multi FIFO Tx is disabled for now. */ + if (!queue && tx_prio) { + u8 x = (skb->data)[5]; + queue = x % config->TxFIFONum; + } + + + off = (u16) mac_control->tx_curr_put_info[queue].offset; + off1 = (u16) mac_control->tx_curr_get_info[queue].offset; + txd_len = mac_control->txdl_len; + txdp = mac_control->txdl_start[queue] + (config->MaxTxDs * off); + + queue_len = mac_control->tx_curr_put_info[queue].fifo_len + 1; + /* Avoid "put" pointer going beyond "get" pointer */ + if (txdp->Host_Control || (((off + 1) % queue_len) == off1)) { + DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n"); + netif_stop_queue(dev); + dev_kfree_skb(skb); + spin_unlock_irqrestore(&sp->tx_lock, flags); + return 0; + } + +#ifdef NETIF_F_TSO + mss = skb_shinfo(skb)->tso_size; + if (mss) { + txdp->Control_1 |= TXD_TCP_LSO_EN; + txdp->Control_1 |= TXD_TCP_LSO_MSS(mss); + } +#endif + + frg_cnt = skb_shinfo(skb)->nr_frags; + frg_len = skb->len - skb->data_len; + + txdp->Host_Control = (unsigned long) skb; + txdp->Buffer_Pointer = pci_map_single + (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE); + if (skb->ip_summed == CHECKSUM_HW) { + txdp->Control_2 |= + (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN | + TXD_TX_CKO_UDP_EN); + } + + txdp->Control_2 |= config->TxIntrType; + + txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) | + TXD_GATHER_CODE_FIRST); + txdp->Control_1 |= TXD_LIST_OWN_XENA; + + /* For fragmented SKB. */ + for (i = 0; i < frg_cnt; i++) { + skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; + txdp++; + txdp->Buffer_Pointer = (u64) pci_map_page + (sp->pdev, frag->page, frag->page_offset, + frag->size, PCI_DMA_TODEVICE); + txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size); + } + txdp->Control_1 |= TXD_GATHER_CODE_LAST; + + tx_fifo = mac_control->tx_FIFO_start[queue]; + val64 = (mac_control->txdl_start_phy[queue] + + (sizeof(TxD_t) * txd_len * off)); + writeq(val64, &tx_fifo->TxDL_Pointer); + + val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | + TX_FIFO_LAST_LIST); +#ifdef NETIF_F_TSO + if (mss) + val64 |= TX_FIFO_SPECIAL_FUNC; +#endif + writeq(val64, &tx_fifo->List_Control); + + off++; + off %= mac_control->tx_curr_put_info[queue].fifo_len + 1; + mac_control->tx_curr_put_info[queue].offset = off; + + /* Avoid "put" pointer going beyond "get" pointer */ + if (((off + 1) % queue_len) == off1) { + DBG_PRINT(TX_DBG, + "No free TxDs for xmit, Put: 0x%x Get:0x%x\n", + off, off1); + netif_stop_queue(dev); + } + + dev->trans_start = jiffies; + spin_unlock_irqrestore(&sp->tx_lock, flags); + + return 0; +} + +/* + * Input Argument/s: + * irq: the irq of the device. + * dev_id: a void pointer to the dev structure of the NIC. + * ptregs: pointer to the registers pushed on the stack. + * Return value: + * void. + * Description: + * This function is the ISR handler of the device. It identifies the reason + * for the interrupt and calls the relevant service routines. + * As a contongency measure, this ISR allocates the recv buffers, if their + * numbers are below the panic value which is presently set to 25% of the + * original number of rcv buffers allocated. + */ + +static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *) dev_id; + nic_t *sp = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; +#ifndef CONFIG_S2IO_NAPI + int i, ret; +#endif + u64 reason = 0, general_mask = 0; + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &sp->mac_control; + config = &sp->config; + + spin_lock(&sp->isr_lock); + + /* Identify the cause for interrupt and call the appropriate + * interrupt handler. Causes for the interrupt could be; + * 1. Rx of packet. + * 2. Tx complete. + * 3. Link down. + * 4. Error in any functional blocks of the NIC. + */ + reason = readq(&bar0->general_int_status); + + if (!reason) { + /* The interrupt was not raised by Xena. */ + spin_unlock(&sp->isr_lock); + return IRQ_NONE; + } + /* Mask the interrupts on the NIC */ + general_mask = readq(&bar0->general_int_mask); + writeq(0xFFFFFFFFFFFFFFFFULL, &bar0->general_int_mask); + +#if DEBUG_ON + sp->int_cnt++; +#endif + + /* If Intr is because of Tx Traffic */ + if (reason & GEN_INTR_TXTRAFFIC) { + txIntrHandler(sp); + } + + /* If Intr is because of an error */ + if (reason & (GEN_ERROR_INTR)) + alarmIntrHandler(sp); + +#ifdef CONFIG_S2IO_NAPI + if (reason & GEN_INTR_RXTRAFFIC) { + if (netif_rx_schedule_prep(dev)) { + en_dis_able_NicIntrs(sp, RX_TRAFFIC_INTR, + DISABLE_INTRS); + /* We retake the snap shot of the general interrupt + * register. + */ + general_mask = readq(&bar0->general_int_mask); + __netif_rx_schedule(dev); + } + } +#else + /* If Intr is because of Rx Traffic */ + if (reason & GEN_INTR_RXTRAFFIC) { + rxIntrHandler(sp); + } +#endif + +/* If the Rx buffer count is below the panic threshold then reallocate the + * buffers from the interrupt handler itself, else schedule a tasklet to + * reallocate the buffers. + */ +#if 1 + for (i = 0; i < config->RxRingNum; i++) { + int rxb_size = atomic_read(&sp->rx_bufs_left[i]); + int level = rx_buffer_level(sp, rxb_size, i); + + if ((level == PANIC) && (!TASKLET_IN_USE)) { + DBG_PRINT(ERR_DBG, "%s: Rx BD hit ", dev->name); + DBG_PRINT(ERR_DBG, "PANIC levels\n"); + if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) { + DBG_PRINT(ERR_DBG, "%s:Out of memory", + dev->name); + DBG_PRINT(ERR_DBG, " in ISR!!\n"); + writeq(general_mask, + &bar0->general_int_mask); + spin_unlock(&sp->isr_lock); + return IRQ_HANDLED; + } + clear_bit(0, + (unsigned long *) (&sp->tasklet_status)); + } else if ((level == LOW) + && (!atomic_read(&sp->tasklet_status))) { + tasklet_schedule(&sp->task); + } + + } +#else + tasklet_schedule(&sp->task); +#endif + + /* Unmask all the previously enabled interrupts on the NIC */ + writeq(general_mask, &bar0->general_int_mask); + + spin_unlock(&sp->isr_lock); + return IRQ_HANDLED; +} + +/* + * Input Argument/s: + * dev - pointer to the device structure. + * Return value: + * pointer to the updated net_device_stats structure. + * Description: + * This function updates the device statistics structure in the s2io_nic + * structure and returns a pointer to the same. + */ +struct net_device_stats *s2io_get_stats(struct net_device *dev) +{ + nic_t *sp = dev->priv; + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &sp->mac_control; + config = &sp->config; + + sp->stats.tx_errors = mac_control->StatsInfo->tmac_any_err_frms; + sp->stats.rx_errors = mac_control->StatsInfo->rmac_drop_frms; + sp->stats.multicast = mac_control->StatsInfo->rmac_vld_mcst_frms; + sp->stats.rx_length_errors = + mac_control->StatsInfo->rmac_long_frms; + + return (&sp->stats); +} + +/* + * Input Argument/s: + * dev - pointer to the device structure + * Return value: + * void. + * Description: + * This function is a driver entry point which gets called by the kernel + * whenever multicast addresses must be enabled/disabled. This also gets + * called to set/reset promiscuous mode. Depending on the deivce flag, we + * determine, if multicast address must be enabled or if promiscuous mode + * is to be disabled etc. + */ +static void s2io_set_multicast(struct net_device *dev) +{ + int i, j, prev_cnt; + struct dev_mc_list *mclist; + nic_t *sp = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = + 0xfeffffffffffULL; + u64 dis_addr = 0xffffffffffffULL, mac_addr = 0; + void *add; + + if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) { + /* Enable all Multicast addresses */ + writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac), + &bar0->rmac_addr_data0_mem); + writeq(RMAC_ADDR_DATA1_MEM_MASK(mask), + &bar0->rmac_addr_data1_mem); + val64 = RMAC_ADDR_CMD_MEM_WE | + RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET); + writeq(val64, &bar0->rmac_addr_cmd_mem); + /* Wait till command completes */ + waitForCmdComplete(sp); + + sp->m_cast_flg = 1; + sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET; + } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) { + /* Disable all Multicast addresses */ + writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), + &bar0->rmac_addr_data0_mem); + val64 = RMAC_ADDR_CMD_MEM_WE | + RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos); + writeq(val64, &bar0->rmac_addr_cmd_mem); + /* Wait till command completes */ + waitForCmdComplete(sp); + + sp->m_cast_flg = 0; + sp->all_multi_pos = 0; + } + + if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) { + /* Put the NIC into promiscuous mode */ + add = (void *) &bar0->mac_cfg; + val64 = readq(&bar0->mac_cfg); + val64 |= MAC_CFG_RMAC_PROM_ENABLE; + + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writel((u32) val64, add); + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writel((u32) (val64 >> 32), (add + 4)); + + val64 = readq(&bar0->mac_cfg); + sp->promisc_flg = 1; + DBG_PRINT(ERR_DBG, "%s: entered promiscuous mode\n", + dev->name); + } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) { + /* Remove the NIC from promiscuous mode */ + add = (void *) &bar0->mac_cfg; + val64 = readq(&bar0->mac_cfg); + val64 &= ~MAC_CFG_RMAC_PROM_ENABLE; + + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writel((u32) val64, add); + writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + writel((u32) (val64 >> 32), (add + 4)); + + val64 = readq(&bar0->mac_cfg); + sp->promisc_flg = 0; + DBG_PRINT(ERR_DBG, "%s: left promiscuous mode\n", + dev->name); + } + + /* Update individual M_CAST address list */ + if ((!sp->m_cast_flg) && dev->mc_count) { + if (dev->mc_count > + (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) { + DBG_PRINT(ERR_DBG, "%s: No more Rx filters ", + dev->name); + DBG_PRINT(ERR_DBG, "can be added, please enable "); + DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n"); + return; + } + + prev_cnt = sp->mc_addr_count; + sp->mc_addr_count = dev->mc_count; + + /* Clear out the previous list of Mc in the H/W. */ + for (i = 0; i < prev_cnt; i++) { + writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), + &bar0->rmac_addr_data0_mem); + val64 = RMAC_ADDR_CMD_MEM_WE | + RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + RMAC_ADDR_CMD_MEM_OFFSET + (MAC_MC_ADDR_START_OFFSET + i); + writeq(val64, &bar0->rmac_addr_cmd_mem); + + /* Wait for command completes */ + if (waitForCmdComplete(sp)) { + DBG_PRINT(ERR_DBG, "%s: Adding ", + dev->name); + DBG_PRINT(ERR_DBG, "Multicasts failed\n"); + return; + } + } + + /* Create the new Rx filter list and update the same in H/W. */ + for (i = 0, mclist = dev->mc_list; i < dev->mc_count; + i++, mclist = mclist->next) { + memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr, + ETH_ALEN); + for (j = 0; j < ETH_ALEN; j++) { + mac_addr |= mclist->dmi_addr[j]; + mac_addr <<= 8; + } + writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), + &bar0->rmac_addr_data0_mem); + + val64 = RMAC_ADDR_CMD_MEM_WE | + RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + RMAC_ADDR_CMD_MEM_OFFSET + (i + MAC_MC_ADDR_START_OFFSET); + writeq(val64, &bar0->rmac_addr_cmd_mem); + + /* Wait for command completes */ + if (waitForCmdComplete(sp)) { + DBG_PRINT(ERR_DBG, "%s: Adding ", + dev->name); + DBG_PRINT(ERR_DBG, "Multicasts failed\n"); + return; + } + } + } +} + +/* + * Input Argument/s: + * dev - pointer to the device structure. + * new_mac - a uchar pointer to the new mac address which is to be set. + * Return value: + * SUCCESS on success and an appropriate (-)ve integer as defined in errno.h + * file on failure. + * Description: + * This procedure will program the Xframe to receive frames with new + * Mac Address + */ +int s2io_set_mac_addr(struct net_device *dev, u8 * addr) +{ + nic_t *sp = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + register u64 val64, mac_addr = 0; + int i; + + /* + * Set the new MAC address as the new unicast filter and reflect this + * change on the device address registered with the OS. It will be + * at offset 0. + */ + for (i = 0; i < ETH_ALEN; i++) { + mac_addr <<= 8; + mac_addr |= addr[i]; + } + + writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), + &bar0->rmac_addr_data0_mem); + + val64 = + RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + RMAC_ADDR_CMD_MEM_OFFSET(0); + writeq(val64, &bar0->rmac_addr_cmd_mem); + /* Wait till command completes */ + if (waitForCmdComplete(sp)) { + DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name); + return FAILURE; + } + + return SUCCESS; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * info - pointer to the structure with parameters given by ethtool to set + * link information. + * Return value: + * 0 on success. + * Description: + * The function sets different link parameters provided by the user onto + * the NIC. + */ +static int s2io_ethtool_sset(struct net_device *dev, + struct ethtool_cmd *info) +{ + nic_t *sp = dev->priv; + if ((info->autoneg == AUTONEG_ENABLE) || + (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL)) + return -EINVAL; + else { + s2io_close(sp->dev); + s2io_open(sp->dev); + } + + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * info - pointer to the structure with parameters given by ethtool to return + * link information. + * Return value: + * void + * Description: + * Returns link specefic information like speed, duplex etc.. to ethtool. + */ +int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info) +{ + nic_t *sp = dev->priv; + info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); + info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); + info->port = PORT_FIBRE; + /* info->transceiver?? TODO */ + + if (netif_carrier_ok(sp->dev)) { + info->speed = 10000; + info->duplex = DUPLEX_FULL; + } else { + info->speed = -1; + info->duplex = -1; + } + + info->autoneg = AUTONEG_DISABLE; + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * info - pointer to the structure with parameters given by ethtool to return + * driver information. + * Return value: + * void + * Description: + * Returns driver specefic information like name, version etc.. to ethtool. + */ +static void s2io_ethtool_gdrvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + nic_t *sp = dev->priv; + + strncpy(info->driver, s2io_driver_name, sizeof(s2io_driver_name)); + strncpy(info->version, s2io_driver_version, + sizeof(s2io_driver_version)); + strncpy(info->fw_version, "", 32); + strncpy(info->bus_info, sp->pdev->slot_name, 32); + info->regdump_len = XENA_REG_SPACE; + info->eedump_len = XENA_EEPROM_SPACE; + info->testinfo_len = S2IO_TEST_LEN; + info->n_stats = S2IO_STAT_LEN; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * regs - pointer to the structure with parameters given by ethtool for + * dumping the registers. + * reg_space - The input argumnet into which all the registers are dumped. + * Return value: + * void + * Description: + * Dumps the entire register space of xFrame NIC into the user given buffer + * area. + */ +static void s2io_ethtool_gregs(struct net_device *dev, + struct ethtool_regs *regs, void *space) +{ + int i; + u64 reg; + u8 *reg_space = (u8 *) space; + nic_t *sp = dev->priv; + + regs->len = XENA_REG_SPACE; + regs->version = sp->pdev->subsystem_device; + + for (i = 0; i < regs->len; i += 8) { + reg = readq((void *) (sp->bar0 + i)); + memcpy((reg_space + i), ®, 8); + } +} + +/* + * Input Argument/s: + * data - address of the private member of the device structure, which + * is a pointer to the s2io_nic structure, provided as an u32. + * Return value: + * void + * Description: + * This is actually the timer function that alternates the adapter LED bit + * of the adapter control bit to set/reset every time on invocation. + * The timer is set for 1/2 a second, hence tha NIC blinks once every second. + */ +static void s2io_phy_id(unsigned long data) +{ + nic_t *sp = (nic_t *) data; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u64 val64 = 0; + u16 subid; + + subid = sp->pdev->subsystem_device; + if ((subid & 0xFF) >= 0x07) { + val64 = readq(&bar0->gpio_control); + val64 ^= GPIO_CTRL_GPIO_0; + writeq(val64, &bar0->gpio_control); + } else { + val64 = readq(&bar0->adapter_control); + val64 ^= ADAPTER_LED_ON; + writeq(val64, &bar0->adapter_control); + } + + mod_timer(&sp->id_timer, jiffies + HZ / 2); +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * id - pointer to the structure with identification parameters given by + * ethtool. + * Return value: + * int , returns '0' on success + * Description: + * Used to physically identify the NIC on the system. The Link LED will blink + * for a time specified by the user for identification. + * NOTE: The Link has to be Up to be able to blink the LED. Hence + * identification is possible only if it's link is up. + */ +static int s2io_ethtool_idnic(struct net_device *dev, u32 data) +{ + u64 val64 = 0; + nic_t *sp = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u16 subid; + + subid = sp->pdev->subsystem_device; + if ((subid & 0xFF) < 0x07) { + val64 = readq(&bar0->adapter_control); + if (!(val64 & ADAPTER_CNTL_EN)) { + printk(KERN_ERR + "Adapter Link down, cannot blink LED\n"); + return -EFAULT; + } + } + if (sp->id_timer.function == NULL) { + init_timer(&sp->id_timer); + sp->id_timer.function = s2io_phy_id; + sp->id_timer.data = (unsigned long) sp; + } + mod_timer(&sp->id_timer, jiffies); + set_current_state(TASK_INTERRUPTIBLE); + if (data) + schedule_timeout(data * HZ); + else + schedule_timeout(MAX_SCHEDULE_TIMEOUT); + del_timer_sync(&sp->id_timer); + + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * ep - pointer to the structure with pause parameters given by ethtool. + * Return value: + * void + * Description: + * Returns the Pause frame generation and reception capability of the NIC. + */ +static void s2io_ethtool_getpause_data(struct net_device *dev, + struct ethtool_pauseparam *ep) +{ + u64 val64; + nic_t *sp = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + + val64 = readq(&bar0->rmac_pause_cfg); + if (val64 & RMAC_PAUSE_GEN_ENABLE) + ep->tx_pause = TRUE; + if (val64 & RMAC_PAUSE_RX_ENABLE) + ep->rx_pause = TRUE; + ep->autoneg = FALSE; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * ep - pointer to the structure with pause parameters given by ethtool. + * Return value: + * int, returns '0' on Success + * Description: + * It can be used to set or reset Pause frame generation or reception support + * of the NIC. + */ +int s2io_ethtool_setpause_data(struct net_device *dev, + struct ethtool_pauseparam *ep) +{ + u64 val64; + nic_t *sp = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + + val64 = readq(&bar0->rmac_pause_cfg); + if (ep->tx_pause) + val64 |= RMAC_PAUSE_GEN_ENABLE; + else + val64 &= ~RMAC_PAUSE_GEN_ENABLE; + if (ep->rx_pause) + val64 |= RMAC_PAUSE_RX_ENABLE; + else + val64 &= ~RMAC_PAUSE_RX_ENABLE; + writeq(val64, &bar0->rmac_pause_cfg); + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * off - offset at which the data must be written + * Return value: + * -1 on failure and the value read from the Eeprom if successful. + * Description: + * Will read 4 bytes of data from the user given offset and return the + * read data. + * NOTE: Will allow to read only part of the EEPROM visible through the + * I2C bus. + */ +#define S2IO_DEV_ID 5 +static u32 readEeprom(nic_t * sp, int off) +{ + u32 data = -1, exit_cnt = 0; + u64 val64; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + + val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | + I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ | + I2C_CONTROL_CNTL_START; + writeq(val64, &bar0->i2c_control); + + while (exit_cnt < 5) { + val64 = readq(&bar0->i2c_control); + if (I2C_CONTROL_CNTL_END(val64)) { + data = I2C_CONTROL_GET_DATA(val64); + break; + } + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 20); + exit_cnt++; + } + + return data; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * off - offset at which the data must be written + * data - The data that is to be written + * cnt - Number of bytes of the data that are actually to be written into + * the Eeprom. (max of 3) + * Return value: + * '0' on success, -1 on failure. + * Description: + * Actually writes the relevant part of the data value into the Eeprom + * through the I2C bus. + */ +static int writeEeprom(nic_t * sp, int off, u32 data, int cnt) +{ + int exit_cnt = 0, ret = -1; + u64 val64; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + + val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | + I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) | + I2C_CONTROL_CNTL_START; + writeq(val64, &bar0->i2c_control); + + while (exit_cnt < 5) { + val64 = readq(&bar0->i2c_control); + if (I2C_CONTROL_CNTL_END(val64)) { + if (!(val64 & I2C_CONTROL_NACK)) + ret = 0; + break; + } + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 20); + exit_cnt++; + } + + return ret; +} + +/* + * A helper function used to invert the 4 byte u32 data field + * byte by byte. This will be used by the Read Eeprom function + * for display purposes. + */ +u32 inv(u32 data) +{ + static u32 ret = 0; + + if (data) { + u8 c = data; + ret = ((ret << 8) + c); + data >>= 8; + inv(data); + } + + return ret; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * eeprom - pointer to the user level structure provided by ethtool, + * containing all relevant information. + * data_buf - user defined value to be written into Eeprom. + * Return value: + * int '0' on success + * Description: + * Reads the values stored in the Eeprom at given offset for a given length. + * Stores these values int the input argument data buffer 'data_buf' and + * returns these to the caller (ethtool.) + */ +int s2io_ethtool_geeprom(struct net_device *dev, + struct ethtool_eeprom *eeprom, u8 * data_buf) +{ + u32 data, i, valid; + nic_t *sp = dev->priv; + + eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16); + + if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE)) + eeprom->len = XENA_EEPROM_SPACE - eeprom->offset; + + for (i = 0; i < eeprom->len; i += 4) { + data = readEeprom(sp, eeprom->offset + i); + if (data < 0) { + DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n"); + return -EFAULT; + } + valid = inv(data); + memcpy((data_buf + i), &valid, 4); + } + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * eeprom - pointer to the user level structure provided by ethtool, + * containing all relevant information. + * data_buf - user defined value to be written into Eeprom. + * Return value: + * '0' on success, -EFAULT on failure. + * Description: + * Tries to write the user provided value in the Eeprom, at the offset + * given by the user. + */ +static int s2io_ethtool_seeprom(struct net_device *dev, + struct ethtool_eeprom *eeprom, + u8 * data_buf) +{ + int len = eeprom->len, cnt = 0; + u32 valid = 0, data; + nic_t *sp = dev->priv; + + if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) { + DBG_PRINT(ERR_DBG, + "ETHTOOL_WRITE_EEPROM Err: Magic value "); + DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n", + eeprom->magic); + return -EFAULT; + } + + while (len) { + data = (u32) data_buf[cnt] & 0x000000FF; + if (data) { + valid = (u32) (data << 24); + } else + valid = data; + + if (writeEeprom(sp, (eeprom->offset + cnt), valid, 0)) { + DBG_PRINT(ERR_DBG, + "ETHTOOL_WRITE_EEPROM Err: Cannot "); + DBG_PRINT(ERR_DBG, + "write into the specified offset\n"); + return -EFAULT; + } + cnt++; + len--; + } + + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * data - variable that returns the result of each of the test conducted by + * the driver. + * Return value: + * '0' on success. + * Description: + * Read and write into all clock domains. The NIC has 3 clock domains, + * see that registers in all the three regions are accessible. + */ +static int s2io_registerTest(nic_t * sp, uint64_t * data) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u64 val64 = 0; + int fail = 0; + + val64 = readq(&bar0->pcc_enable); + if (val64 != 0xff00000000000000ULL) { + fail = 1; + DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n"); + } + + val64 = readq(&bar0->rmac_pause_cfg); + if (val64 != 0xc000ffff00000000ULL) { + fail = 1; + DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n"); + } + + val64 = readq(&bar0->rx_queue_cfg); + if (val64 != 0x0808080808080808ULL) { + fail = 1; + DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n"); + } + + val64 = readq(&bar0->xgxs_efifo_cfg); + if (val64 != 0x000000001923141EULL) { + fail = 1; + DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n"); + } + + val64 = 0x5A5A5A5A5A5A5A5AULL; + writeq(val64, &bar0->xmsi_data); + val64 = readq(&bar0->xmsi_data); + if (val64 != 0x5A5A5A5A5A5A5A5AULL) { + fail = 1; + DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n"); + } + + val64 = 0xA5A5A5A5A5A5A5A5ULL; + writeq(val64, &bar0->xmsi_data); + val64 = readq(&bar0->xmsi_data); + if (val64 != 0xA5A5A5A5A5A5A5A5ULL) { + fail = 1; + DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n"); + } + + *data = fail; + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * data - variable that returns the result of each of the test conducted by + * the driver. + * Return value: + * '0' on success. + * Description: + * Verify that EEPROM in the xena can be programmed using I2C_CONTROL + * register. + */ +static int s2io_eepromTest(nic_t * sp, uint64_t * data) +{ + int fail = 0, ret_data; + + /* Test Write Error at offset 0 */ + if (!writeEeprom(sp, 0, 0, 3)) + fail = 1; + + /* Test Write at offset 4f0 */ + if (writeEeprom(sp, 0x4F0, 0x01234567, 3)) + fail = 1; + if ((ret_data = readEeprom(sp, 0x4f0)) < 0) + fail = 1; + + if (ret_data != 0x01234567) + fail = 1; + + /* Reset the EEPROM data go FFFF */ + writeEeprom(sp, 0x4F0, 0xFFFFFFFF, 3); + + /* Test Write Request Error at offset 0x7c */ + if (!writeEeprom(sp, 0x07C, 0, 3)) + fail = 1; + + /* Test Write Request at offset 0x7fc */ + if (writeEeprom(sp, 0x7FC, 0x01234567, 3)) + fail = 1; + if ((ret_data = readEeprom(sp, 0x7FC)) < 0) + fail = 1; + + if (ret_data != 0x01234567) + fail = 1; + + /* Reset the EEPROM data go FFFF */ + writeEeprom(sp, 0x7FC, 0xFFFFFFFF, 3); + + /* Test Write Error at offset 0x80 */ + if (!writeEeprom(sp, 0x080, 0, 3)) + fail = 1; + + /* Test Write Error at offset 0xfc */ + if (!writeEeprom(sp, 0x0FC, 0, 3)) + fail = 1; + + /* Test Write Error at offset 0x100 */ + if (!writeEeprom(sp, 0x100, 0, 3)) + fail = 1; + + /* Test Write Error at offset 4ec */ + if (!writeEeprom(sp, 0x4EC, 0, 3)) + fail = 1; + + *data = fail; + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * data - variable that returns the result of each of the test conducted by + * the driver. + * Return value: + * '0' on success and -1 on failure. + * Description: + * This invokes the MemBist test of the card. We give around + * 2 secs time for the Test to complete. If it's still not complete + * within this peiod, we consider that the test failed. + */ +static int s2io_bistTest(nic_t * sp, uint64_t * data) +{ + u8 bist = 0; + int cnt = 0, ret = -1; + + pci_read_config_byte(sp->pdev, PCI_BIST, &bist); + bist |= PCI_BIST_START; + pci_write_config_word(sp->pdev, PCI_BIST, bist); + + while (cnt < 20) { + pci_read_config_byte(sp->pdev, PCI_BIST, &bist); + if (!(bist & PCI_BIST_START)) { + *data = (bist & PCI_BIST_CODE_MASK); + ret = 0; + break; + } + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 10); + cnt++; + } + + return ret; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * data - variable that returns the result of each of the test conducted by + * the driver. + * Return value: + * '0' on success. + * Description: + * The function verifies the link state of the NIC and updates the input + * argument 'data' appropriately. + */ +static int s2io_linkTest(nic_t * sp, uint64_t * data) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u64 val64; + + val64 = readq(&bar0->adapter_status); + if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT) + *data = 1; + + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * data - variable that returns the result of each of the test conducted by + * the driver. + * Return value: + * '0' on success. + * Description: + * This is one of the offline test that tests the read and write + * access to the RldRam chip on the NIC. + */ +static int s2io_rldramTest(nic_t * sp, uint64_t * data) +{ + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + u64 val64; + int cnt, iteration = 0, test_pass = 0; + + val64 = readq(&bar0->adapter_control); + val64 &= ~ADAPTER_ECC_EN; + writeq(val64, &bar0->adapter_control); + + val64 = readq(&bar0->mc_rldram_test_ctrl); + val64 |= MC_RLDRAM_TEST_MODE; + writeq(val64, &bar0->mc_rldram_test_ctrl); + + val64 = readq(&bar0->mc_rldram_mrs); + val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE; + writeq(val64, &bar0->mc_rldram_mrs); + + val64 |= MC_RLDRAM_MRS_ENABLE; + writeq(val64, &bar0->mc_rldram_mrs); + + while (iteration < 2) { + val64 = 0x55555555aaaa0000ULL; + if (iteration == 1) { + val64 ^= 0xFFFFFFFFFFFF0000ULL; + } + writeq(val64, &bar0->mc_rldram_test_d0); + + val64 = 0xaaaa5a5555550000ULL; + if (iteration == 1) { + val64 ^= 0xFFFFFFFFFFFF0000ULL; + } + writeq(val64, &bar0->mc_rldram_test_d1); + + val64 = 0x55aaaaaaaa5a0000ULL; + if (iteration == 1) { + val64 ^= 0xFFFFFFFFFFFF0000ULL; + } + writeq(val64, &bar0->mc_rldram_test_d2); + + val64 = (u64) (0x0000003fffff0000ULL); + writeq(val64, &bar0->mc_rldram_test_add); + + + val64 = MC_RLDRAM_TEST_MODE; + writeq(val64, &bar0->mc_rldram_test_ctrl); + + val64 |= + MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE | + MC_RLDRAM_TEST_GO; + writeq(val64, &bar0->mc_rldram_test_ctrl); + + for (cnt = 0; cnt < 5; cnt++) { + val64 = readq(&bar0->mc_rldram_test_ctrl); + if (val64 & MC_RLDRAM_TEST_DONE) + break; + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 5); + } + + if (cnt == 5) + break; + + val64 = MC_RLDRAM_TEST_MODE; + writeq(val64, &bar0->mc_rldram_test_ctrl); + + val64 |= MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO; + writeq(val64, &bar0->mc_rldram_test_ctrl); + + for (cnt = 0; cnt < 5; cnt++) { + val64 = readq(&bar0->mc_rldram_test_ctrl); + if (val64 & MC_RLDRAM_TEST_DONE) + break; + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 2); + } + + if (cnt == 5) + break; + + val64 = readq(&bar0->mc_rldram_test_ctrl); + if (val64 & MC_RLDRAM_TEST_PASS) + test_pass = 1; + + iteration++; + } + + if (!test_pass) + *data = 1; + else + *data = 0; + + return 0; +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * ethtest - pointer to a ethtool command specific structure that will be + * returned to the user. + * data - variable that returns the result of each of the test conducted by + * the driver. + * Return value: + * SUCCESS on success and an appropriate -1 on failure. + * Description: + * This function conducts 6 tests ( 4 offline and 2 online) to determine + * the health of the card. + */ +static void s2io_ethtool_test(struct net_device *dev, + struct ethtool_test *ethtest, + uint64_t * data) +{ + nic_t *sp = dev->priv; + int orig_state = netif_running(sp->dev); + + if (ethtest->flags == ETH_TEST_FL_OFFLINE) { + /* Offline Tests. */ + if (orig_state) { + s2io_close(sp->dev); + s2io_set_swapper(sp); + } else + s2io_set_swapper(sp); + + if (s2io_registerTest(sp, &data[0])) + ethtest->flags |= ETH_TEST_FL_FAILED; + + s2io_reset(sp); + s2io_set_swapper(sp); + + if (s2io_rldramTest(sp, &data[3])) + ethtest->flags |= ETH_TEST_FL_FAILED; + + s2io_reset(sp); + s2io_set_swapper(sp); + + if (s2io_eepromTest(sp, &data[1])) + ethtest->flags |= ETH_TEST_FL_FAILED; + + if (s2io_bistTest(sp, &data[4])) + ethtest->flags |= ETH_TEST_FL_FAILED; + + if (orig_state) + s2io_open(sp->dev); + + data[2] = 0; + } else { + /* Online Tests. */ + if (!orig_state) { + DBG_PRINT(ERR_DBG, + "%s: is not up, cannot run test\n", + dev->name); + data[0] = -1; + data[1] = -1; + data[2] = -1; + data[3] = -1; + data[4] = -1; + } + + if (s2io_linkTest(sp, &data[2])) + ethtest->flags |= ETH_TEST_FL_FAILED; + + data[0] = 0; + data[1] = 0; + data[3] = 0; + data[4] = 0; + } +} + +static void s2io_get_ethtool_stats(struct net_device *dev, + struct ethtool_stats *estats, + u64 * tmp_stats) +{ + int i = 0; + nic_t *sp = dev->priv; + StatInfo_t *stat_info = sp->mac_control.StatsInfo; + + tmp_stats[i++] = stat_info->tmac_frms; + tmp_stats[i++] = stat_info->tmac_data_octets; + tmp_stats[i++] = stat_info->tmac_drop_frms; + tmp_stats[i++] = stat_info->tmac_mcst_frms; + tmp_stats[i++] = stat_info->tmac_bcst_frms; + tmp_stats[i++] = stat_info->tmac_pause_ctrl_frms; + tmp_stats[i++] = stat_info->tmac_any_err_frms; + tmp_stats[i++] = stat_info->tmac_vld_ip_octets; + tmp_stats[i++] = stat_info->tmac_vld_ip; + tmp_stats[i++] = stat_info->tmac_drop_ip; + tmp_stats[i++] = stat_info->tmac_icmp; + tmp_stats[i++] = stat_info->tmac_rst_tcp; + tmp_stats[i++] = stat_info->tmac_tcp; + tmp_stats[i++] = stat_info->tmac_udp; + tmp_stats[i++] = stat_info->rmac_vld_frms; + tmp_stats[i++] = stat_info->rmac_data_octets; + tmp_stats[i++] = stat_info->rmac_fcs_err_frms; + tmp_stats[i++] = stat_info->rmac_drop_frms; + tmp_stats[i++] = stat_info->rmac_vld_mcst_frms; + tmp_stats[i++] = stat_info->rmac_vld_bcst_frms; + tmp_stats[i++] = stat_info->rmac_in_rng_len_err_frms; + tmp_stats[i++] = stat_info->rmac_long_frms; + tmp_stats[i++] = stat_info->rmac_pause_ctrl_frms; + tmp_stats[i++] = stat_info->rmac_discarded_frms; + tmp_stats[i++] = stat_info->rmac_usized_frms; + tmp_stats[i++] = stat_info->rmac_osized_frms; + tmp_stats[i++] = stat_info->rmac_frag_frms; + tmp_stats[i++] = stat_info->rmac_jabber_frms; + tmp_stats[i++] = stat_info->rmac_ip; + tmp_stats[i++] = stat_info->rmac_ip_octets; + tmp_stats[i++] = stat_info->rmac_hdr_err_ip; + tmp_stats[i++] = stat_info->rmac_drop_ip; + tmp_stats[i++] = stat_info->rmac_icmp; + tmp_stats[i++] = stat_info->rmac_tcp; + tmp_stats[i++] = stat_info->rmac_udp; + tmp_stats[i++] = stat_info->rmac_err_drp_udp; + tmp_stats[i++] = stat_info->rmac_pause_cnt; + tmp_stats[i++] = stat_info->rmac_accepted_ip; + tmp_stats[i++] = stat_info->rmac_err_tcp; +} + +int s2io_ethtool_get_regs_len(struct net_device *dev) +{ + return (XENA_REG_SPACE); +} + + +u32 s2io_ethtool_get_rx_csum(struct net_device * dev) +{ + nic_t *sp = dev->priv; + + return (sp->rx_csum); +} +int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data) +{ + nic_t *sp = dev->priv; + + if (data) + sp->rx_csum = 1; + else + sp->rx_csum = 0; + + return 0; +} +int s2io_get_eeprom_len(struct net_device *dev) +{ + return (XENA_EEPROM_SPACE); +} + +int s2io_ethtool_self_test_count(struct net_device *dev) +{ + return (S2IO_TEST_LEN); +} +void s2io_ethtool_get_strings(struct net_device *dev, + u32 stringset, u8 * data) +{ + switch (stringset) { + case ETH_SS_TEST: + memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN); + break; + case ETH_SS_STATS: + memcpy(data, ðtool_stats_keys, + sizeof(ethtool_stats_keys)); + } +} +static int s2io_ethtool_get_stats_count(struct net_device *dev) +{ + return (S2IO_STAT_LEN); +} + +static struct ethtool_ops netdev_ethtool_ops = { + .get_settings = s2io_ethtool_gset, + .set_settings = s2io_ethtool_sset, + .get_drvinfo = s2io_ethtool_gdrvinfo, + .get_regs_len = s2io_ethtool_get_regs_len, + .get_regs = s2io_ethtool_gregs, + .get_link = ethtool_op_get_link, + .get_eeprom_len = s2io_get_eeprom_len, + .get_eeprom = s2io_ethtool_geeprom, + .set_eeprom = s2io_ethtool_seeprom, + .get_pauseparam = s2io_ethtool_getpause_data, + .set_pauseparam = s2io_ethtool_setpause_data, + .get_rx_csum = s2io_ethtool_get_rx_csum, + .set_rx_csum = s2io_ethtool_set_rx_csum, + .get_tx_csum = ethtool_op_get_tx_csum, + .set_tx_csum = ethtool_op_set_tx_csum, + .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, +#ifdef NETIF_F_TSO + .get_tso = ethtool_op_get_tso, + .set_tso = ethtool_op_set_tso, +#endif + .self_test_count = s2io_ethtool_self_test_count, + .self_test = s2io_ethtool_test, + .get_strings = s2io_ethtool_get_strings, + .phys_id = s2io_ethtool_idnic, + .get_stats_count = s2io_ethtool_get_stats_count, + .get_ethtool_stats = s2io_get_ethtool_stats +}; + +/* + * Input Argument/s: + * dev - Device pointer. + * ifr - An IOCTL specefic structure, that can contain a pointer to + * a proprietary structure used to pass information to the driver. + * cmd - This is used to distinguish between the different commands that + * can be passed to the IOCTL functions. + * Return value: + * '0' on success and an appropriate (-)ve integer as defined in errno.h + * file on failure. + * Description: + * This function has support for ethtool, adding multiple MAC addresses on + * the NIC and some DBG commands for the util tool. + */ +int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + return -EOPNOTSUPP; +} + +/* + * Input Argument/s: + * dev - device pointer. + * new_mtu - the new MTU size for the device. + * Return value: + * '0' on success and an appropriate (-)ve integer as defined in errno.h + * file on failure. + * Description: + * A driver entry point to change MTU size for the device. Before changing + * the MTU the device must be stopped. + */ +int s2io_change_mtu(struct net_device *dev, int new_mtu) +{ + nic_t *sp = dev->priv; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; + register u64 val64; + + if (netif_running(dev)) { + DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name); + DBG_PRINT(ERR_DBG, "change its MTU \n"); + return -EBUSY; + } + + if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) { + DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", + dev->name); + return -EPERM; + } + +/* Set the new MTU into the PYLD register of the NIC */ + val64 = new_mtu; + writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); + + dev->mtu = new_mtu; + + return 0; +} + +/* + * Input Argument/s: + * dev_adr - address of the device structure in dma_addr_t format. + * Return value: + * void. + * Description: + * This is the tasklet or the bottom half of the ISR. This is + * an extension of the ISR which is scheduled by the scheduler to be run + * when the load on the CPU is low. All low priority tasks of the ISR can + * be pushed into the tasklet. For now the tasklet is used only to + * replenish the Rx buffers in the Rx buffer descriptors. + */ +static void s2io_tasklet(unsigned long dev_addr) +{ + struct net_device *dev = (struct net_device *) dev_addr; + nic_t *sp = dev->priv; + int i, ret; + mac_info_t *mac_control; + struct config_param *config; + + mac_control = &sp->mac_control; + config = &sp->config; + + if (!TASKLET_IN_USE) { + for (i = 0; i < config->RxRingNum; i++) { + ret = fill_rx_buffers(sp, i); + if (ret == -ENOMEM) { + DBG_PRINT(ERR_DBG, "%s: Out of ", + dev->name); + DBG_PRINT(ERR_DBG, "memory in tasklet\n"); + return; + } else if (ret == -EFILL) { + DBG_PRINT(ERR_DBG, + "%s: Rx Ring %d is full\n", + dev->name, i); + return; + } + } + clear_bit(0, (unsigned long *) (&sp->tasklet_status)); + } +} + + +/* + * Description: + * + */ +static void s2io_set_link(unsigned long data) +{ + nic_t *nic = (nic_t *) data; + struct net_device *dev = nic->dev; + XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; + register u64 val64, err_reg; + + /* Allow a small delay for the NICs self initiated + * cleanup to complete. + */ + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(HZ / 10); + + val64 = readq(&bar0->adapter_status); + if (verify_xena_quiescence(val64, nic->device_enabled_once)) { + /* Acknowledge interrupt and clear the R1 register */ + err_reg = readq(&bar0->mac_rmac_err_reg); + writeq(err_reg, &bar0->mac_rmac_err_reg); + + if (LINK_IS_UP(val64)) { + val64 = readq(&bar0->adapter_control); + val64 |= ADAPTER_CNTL_EN; + writeq(val64, &bar0->adapter_control); + val64 |= ADAPTER_LED_ON; + writeq(val64, &bar0->adapter_control); + val64 = readq(&bar0->adapter_status); + if (!LINK_IS_UP(val64)) { + DBG_PRINT(ERR_DBG, "%s:", dev->name); + DBG_PRINT(ERR_DBG, " Link down"); + DBG_PRINT(ERR_DBG, "after "); + DBG_PRINT(ERR_DBG, "enabling "); + DBG_PRINT(ERR_DBG, "device \n"); + } + if (nic->device_enabled_once == FALSE) { + nic->device_enabled_once = TRUE; + } + s2io_link(nic, LINK_UP); + } else { + s2io_link(nic, LINK_DOWN); + } + } else { /* NIC is not Quiescent. */ + DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name); + DBG_PRINT(ERR_DBG, "device is not Quiescent\n"); + netif_stop_queue(dev); + } +} + +/* + * Description: + * This function is scheduled to be run by the s2io_tx_watchdog + * function after 0.5 secs to reset the NIC. The idea is to reduce + * the run time of the watch dog routine which is run holding a + * spin lock. + */ +static void s2io_restart_nic(unsigned long data) +{ + struct net_device *dev = (struct net_device *) data; + nic_t *sp = dev->priv; + + s2io_close(dev); + sp->device_close_flag = TRUE; + s2io_open(dev); + DBG_PRINT(ERR_DBG, + "%s: was reset by Tx watchdog timer.\n", dev->name); +} + +/* + * Input Argument/s: + * dev - device pointer. + * Return value: + * void + * Description: + * This function is triggered if the Tx Queue is stopped + * for a pre-defined amount of time when the Interface is still up. + * If the Interface is jammed in such a situation, the hardware is + * reset (by s2io_close) and restarted again (by s2io_open) to + * overcome any problem that might have been caused in the hardware. + */ +static void s2io_tx_watchdog(struct net_device *dev) +{ + nic_t *sp = dev->priv; + + if (netif_carrier_ok(dev)) { + schedule_work(&sp->rst_timer_task); + } +} + +/* + * Input Argument/s: + * sp - private member of the device structure, which is a pointer to the + * s2io_nic structure. + * skb - the socket buffer pointer. + * len - length of the packet + * cksum - FCS checksum of the frame. + * ring_no - the ring from which this RxD was extracted. + * Return value: + * SUCCESS on success and -1 on failure. + * Description: + * This function is called by the Tx interrupt serivce routine to perform + * some OS related operations on the SKB before passing it to the upper + * layers. It mainly checks if the checksum is OK, if so adds it to the + * SKBs cksum variable, increments the Rx packet count and passes the SKB + * to the upper layer. If the checksum is wrong, it increments the Rx + * packet error count, frees the SKB and returns error. + */ +static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no) +{ + struct net_device *dev = (struct net_device *) sp->dev; + struct sk_buff *skb = + (struct sk_buff *) ((unsigned long) rxdp->Host_Control); + u16 l3_csum, l4_csum; + + l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1); + if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && (sp->rx_csum)) { + l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1); + if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) { + /* NIC verifies if the Checksum of the received + * frame is Ok or not and accordingly returns + * a flag in the RxD. + */ + skb->ip_summed = CHECKSUM_UNNECESSARY; + } else { + /* + * Packet with erroneous checksum, let the + * upper layers deal with it. + */ + skb->ip_summed = CHECKSUM_NONE; + } + } else { + skb->ip_summed = CHECKSUM_NONE; + } + + skb->dev = dev; + skb_put(skb, len); + skb->protocol = eth_type_trans(skb, dev); + +#ifdef CONFIG_S2IO_NAPI + netif_receive_skb(skb); +#else + netif_rx(skb); +#endif + + dev->last_rx = jiffies; +#if DEBUG_ON + sp->rxpkt_cnt++; +#endif + sp->rx_pkt_count++; + sp->stats.rx_packets++; + sp->stats.rx_bytes += len; + sp->rxpkt_bytes += len; + + atomic_dec(&sp->rx_bufs_left[ring_no]); + rxdp->Host_Control = 0; + return SUCCESS; +} + +int check_for_txSpace(nic_t * sp) +{ + u32 put_off, get_off, queue_len; + int ret = TRUE, i; + + for (i = 0; i < sp->config.TxFIFONum; i++) { + queue_len = sp->mac_control.tx_curr_put_info[i].fifo_len + + 1; + put_off = sp->mac_control.tx_curr_put_info[i].offset; + get_off = sp->mac_control.tx_curr_get_info[i].offset; + if (((put_off + 1) % queue_len) == get_off) { + ret = FALSE; + break; + } + } + + return ret; +} + +/* +* Input Argument/s: +* sp - private member of the device structure, which is a pointer to the +* s2io_nic structure. +* link - inidicates whether link is UP/DOWN. +* Return value: +* void. +* Description: +* This function stops/starts the Tx queue depending on whether the link +* status of the NIC is is down or up. This is called by the Alarm interrupt +* handler whenever a link change interrupt comes up. +*/ +void s2io_link(nic_t * sp, int link) +{ + struct net_device *dev = (struct net_device *) sp->dev; + + if (link != sp->last_link_state) { + if (link == LINK_DOWN) { + DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name); + netif_carrier_off(dev); + netif_stop_queue(dev); + } else { + DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name); + netif_carrier_on(dev); + if (check_for_txSpace(sp) == TRUE) { + /* Don't wake the queue, if we know there + * are no free TxDs available. + */ + netif_wake_queue(dev); + } + } + } + sp->last_link_state = link; +} + +/* +* Input Argument/s: +* pdev - structure containing the PCI related information of the device. +* Return value: +* returns the revision ID of the device. +* Description: +* Function to identify the Revision ID of xena. +*/ +int get_xena_rev_id(struct pci_dev *pdev) +{ + u8 id = 0; + int ret; + ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id); + return id; +} + +/* +* Input Argument/s: +* sp - private member of the device structure, which is a pointer to the +* s2io_nic structure. +* Return value: +* void +* Description: +* This function initializes a few of the PCI and PCI-X configuration registers +* with recommended values. +*/ +static void s2io_init_pci(nic_t * sp) +{ + u16 pci_cmd = 0; + +/* Enable Data Parity Error Recovery in PCI-X command register. */ + pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, + &(sp->pcix_cmd)); + pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, + (sp->pcix_cmd | 1)); + pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, + &(sp->pcix_cmd)); + +/* Set the PErr Response bit in PCI command register. */ + pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); + pci_write_config_word(sp->pdev, PCI_COMMAND, + (pci_cmd | PCI_COMMAND_PARITY)); + pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); + +/* Set user specified value in Latency Timer */ + if (latency_timer) { + pci_write_config_byte(sp->pdev, PCI_LATENCY_TIMER, + latency_timer); + pci_read_config_byte(sp->pdev, PCI_LATENCY_TIMER, + &latency_timer); + } + +/* Set MMRB count to 4096 in PCI-X Command register. */ + pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, + (sp->pcix_cmd | 0x0C)); + pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, + &(sp->pcix_cmd)); + +/* Setting Maximum outstanding splits to two for now. */ + sp->pcix_cmd &= 0xFF1F; + + sp->pcix_cmd |= + XENA_MAX_OUTSTANDING_SPLITS(XENA_TWO_SPLIT_TRANSACTION); + pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, + sp->pcix_cmd); + pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, + &(sp->pcix_cmd)); + +} + +MODULE_AUTHOR("Raghavendra Koushik "); +MODULE_LICENSE("GPL"); +MODULE_PARM(ring_num, "1-" __MODULE_STRING(1) "i"); +MODULE_PARM(frame_len, "1-" __MODULE_STRING(8) "i"); +MODULE_PARM(ring_len, "1-" __MODULE_STRING(8) "i"); +MODULE_PARM(fifo_num, "1-" __MODULE_STRING(1) "i"); +MODULE_PARM(fifo_len, "1-" __MODULE_STRING(8) "i"); +MODULE_PARM(rx_prio, "1-" __MODULE_STRING(1) "i"); +MODULE_PARM(tx_prio, "1-" __MODULE_STRING(1) "i"); +MODULE_PARM(latency_timer, "1-" __MODULE_STRING(1) "i"); + +/* +* Input Argument/s: +* pdev - structure containing the PCI related information of the device. +* pre - the List of PCI devices supported by the driver listed in s2io_tbl. +* Return value: +* returns '0' on success and negative on failure. +* Description: +* The function initializes an adapter identified by the pci_dec structure. +* All OS related initialization including memory and device structure and +* initlaization of the device private variable is done. Also the swapper +* control register is initialized to enable read and write into the I/O +* registers of the device. +* +*/ +static int __devinit +s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) +{ + nic_t *sp; + struct net_device *dev; + char *dev_name = "S2IO 10GE NIC"; + int i, j, ret; + int dma_flag = FALSE; + u32 mac_up, mac_down; + u64 val64 = 0, tmp64 = 0; + XENA_dev_config_t *bar0 = NULL; + u16 subid; + mac_info_t *mac_control; + struct config_param *config; + + + if ((ret = pci_enable_device(pdev))) { + DBG_PRINT(ERR_DBG, + "s2io_init_nic: pci_enable_device failed\n"); + return ret; + } + + if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) { + DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n"); + dma_flag = TRUE; + if (pci_set_consistent_dma_mask + (pdev, 0xffffffffffffffffULL)) { + DBG_PRINT(ERR_DBG, + "Unable to obtain 64bit DMA for \ + consistent allocations\n"); + pci_disable_device(pdev); + return -ENOMEM; + } + } else if (!pci_set_dma_mask(pdev, 0xffffffffUL)) { + DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n"); + } else { + pci_disable_device(pdev); + return -ENOMEM; + } + + if (pci_request_regions(pdev, s2io_driver_name)) { + DBG_PRINT(ERR_DBG, "Request Regions failed\n"), + pci_disable_device(pdev); + return -ENODEV; + } + + dev = alloc_etherdev(sizeof(nic_t)); + if (dev == NULL) { + DBG_PRINT(ERR_DBG, "Device allocation failed\n"); + pci_disable_device(pdev); + pci_release_regions(pdev); + return -ENODEV; + } + + pci_set_master(pdev); + pci_set_drvdata(pdev, dev); + SET_MODULE_OWNER(dev); + SET_NETDEV_DEV(dev, &pdev->dev); + + /* Private member variable initialized to s2io NIC structure */ + sp = dev->priv; + memset(sp, 0, sizeof(nic_t)); + sp->dev = dev; + sp->pdev = pdev; + sp->vendor_id = pdev->vendor; + sp->device_id = pdev->device; + sp->high_dma_flag = dma_flag; + sp->irq = pdev->irq; + sp->device_enabled_once = FALSE; + strcpy(sp->name, dev_name); + + /* Initialize some PCI/PCI-X fields of the NIC. */ + s2io_init_pci(sp); + + /* Setting the device configuration parameters. + * Most of these parameters can be specified by the user during + * module insertion as they are module loadable parameters. If + * these parameters are not not specified during load time, they + * are initialized with default values. + */ + mac_control = &sp->mac_control; + config = &sp->config; + + /* Tx side parameters. */ + config->TxFIFONum = fifo_num ? fifo_num : 1; + + if (!fifo_len[0] && (fifo_num > 1)) { + printk(KERN_ERR "Fifo Lens not specified for all FIFOs\n"); + goto init_failed; + } + + if (fifo_len[0]) { + int cnt; + + for (cnt = 0; fifo_len[cnt]; cnt++); + if (fifo_num) { + if (cnt < fifo_num) { + printk(KERN_ERR + "Fifo Lens not specified for "); + printk(KERN_ERR "all FIFOs\n"); + goto init_failed; + } + } + for (cnt = 0; cnt < config->TxFIFONum; cnt++) { + config->TxCfg[cnt].FifoLen = fifo_len[cnt]; + config->TxCfg[cnt].FifoPriority = cnt; + } + } else { + config->TxCfg[0].FifoLen = DEFAULT_FIFO_LEN; + config->TxCfg[0].FifoPriority = 0; + } + + config->TxIntrType = TXD_INT_TYPE_UTILZ; + for (i = 0; i < config->TxFIFONum; i++) { + if (config->TxCfg[i].FifoLen < 65) { + config->TxIntrType = TXD_INT_TYPE_PER_LIST; + break; + } + } + + config->TxCfg[0].fNoSnoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER); + config->MaxTxDs = MAX_SKB_FRAGS; + config->TxFlow = TRUE; + + /* Rx side parameters. */ + config->RxRingNum = ring_num ? ring_num : 1; + + if (ring_len[0]) { + int cnt; + for (cnt = 0; cnt < config->RxRingNum; cnt++) { + config->RxCfg[cnt].NumRxd = ring_len[cnt]; + config->RxCfg[cnt].RingPriority = cnt; + } + } else { + int id; + if ((id = get_xena_rev_id(pdev)) == 1) { + config->RxCfg[0].NumRxd = LARGE_RXD_CNT; + + } else { + config->RxCfg[0].NumRxd = SMALL_RXD_CNT; + } + config->RxCfg[0].RingPriority = 0; + } + config->RxCfg[0].RingOrg = RING_ORG_BUFF1; + config->RxCfg[0].RxdThresh = DEFAULT_RXD_THRESHOLD; + config->RxCfg[0].fNoSnoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER); + config->RxCfg[0].RxD_BackOff_Interval = TBD; + config->RxFlow = TRUE; + + /* Miscellaneous parameters. */ + config->RxVLANEnable = TRUE; + config->MTU = MAX_MTU_VLAN; + config->JumboEnable = FALSE; + + /* Setting Mac Control parameters */ + mac_control->txdl_len = MAX_SKB_FRAGS; + mac_control->rmac_pause_time = 0; + + /* Initialize Ring buffer parameters. */ + for (i = 0; i < config->RxRingNum; i++) + atomic_set(&sp->rx_bufs_left[i], 0); + + /* initialize the shared memory used by the NIC and the host */ + if (initSharedMem(sp)) { + DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", + dev->name); + goto mem_alloc_failed; + } + + sp->bar0 = (caddr_t) ioremap(pci_resource_start(pdev, 0), + pci_resource_len(pdev, 0)); + if (!sp->bar0) { + DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n", + dev->name); + goto bar0_remap_failed; + } + + sp->bar1 = (caddr_t) ioremap(pci_resource_start(pdev, 2), + pci_resource_len(pdev, 2)); + if (!sp->bar1) { + DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n", + dev->name); + goto bar1_remap_failed; + } + + dev->irq = pdev->irq; + dev->base_addr = (unsigned long) sp->bar0; + + /* Initializing the BAR1 address as the start of the FIFO pointer. */ + for (j = 0; j < MAX_TX_FIFOS; j++) { + mac_control->tx_FIFO_start[j] = (TxFIFO_element_t *) + (sp->bar1 + (j * 0x00020000)); + } + + /* Driver entry points */ + dev->open = &s2io_open; + dev->stop = &s2io_close; + dev->hard_start_xmit = &s2io_xmit; + dev->get_stats = &s2io_get_stats; + dev->set_multicast_list = &s2io_set_multicast; + dev->do_ioctl = &s2io_ioctl; + dev->change_mtu = &s2io_change_mtu; + SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); + + /* + * will use eth_mac_addr() for dev->set_mac_address + * mac address will be set every time dev->open() is called + */ +#ifdef CONFIG_S2IO_NAPI + dev->poll = s2io_poll; + dev->weight = 128; /* For now. */ +#endif + + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + if (sp->high_dma_flag == TRUE) + dev->features |= NETIF_F_HIGHDMA; +#ifdef NETIF_F_TSO + dev->features |= NETIF_F_TSO; +#endif + + dev->tx_timeout = &s2io_tx_watchdog; + dev->watchdog_timeo = WATCH_DOG_TIMEOUT; + INIT_WORK(&sp->rst_timer_task, + (void (*)(void *)) s2io_restart_nic, dev); + INIT_WORK(&sp->set_link_task, + (void (*)(void *)) s2io_set_link, sp); + + if (register_netdev(dev)) { + DBG_PRINT(ERR_DBG, "Device registration failed\n"); + goto register_failed; + } + + pci_save_state(sp->pdev, sp->config_space); + + /* Setting swapper control on the NIC, for proper reset operation */ + if (s2io_set_swapper(sp)) { + DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n", + dev->name); + goto set_swap_failed; + } + + /* Fix for all "FFs" MAC address problems observed on Alpha platforms */ + FixMacAddress(sp); + s2io_reset(sp); + + /* Setting swapper control on the NIC, so the MAC address can be read. + */ + if (s2io_set_swapper(sp)) { + DBG_PRINT(ERR_DBG, + "%s: S2IO: swapper settings are wrong\n", + dev->name); + goto set_swap_failed; + } + + /* MAC address initialization. + * For now only one mac address will be read and used. + */ + bar0 = (XENA_dev_config_t *) sp->bar0; + val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET); + writeq(val64, &bar0->rmac_addr_cmd_mem); + waitForCmdComplete(sp); + + tmp64 = readq(&bar0->rmac_addr_data0_mem); + mac_down = (u32) tmp64; + mac_up = (u32) (tmp64 >> 32); + + memset(sp->defMacAddr[0].mac_addr, 0, sizeof(ETH_ALEN)); + + sp->defMacAddr[0].mac_addr[3] = (u8) (mac_up); + sp->defMacAddr[0].mac_addr[2] = (u8) (mac_up >> 8); + sp->defMacAddr[0].mac_addr[1] = (u8) (mac_up >> 16); + sp->defMacAddr[0].mac_addr[0] = (u8) (mac_up >> 24); + sp->defMacAddr[0].mac_addr[5] = (u8) (mac_down >> 16); + sp->defMacAddr[0].mac_addr[4] = (u8) (mac_down >> 24); + + DBG_PRINT(INIT_DBG, + "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n", + sp->defMacAddr[0].mac_addr[0], + sp->defMacAddr[0].mac_addr[1], + sp->defMacAddr[0].mac_addr[2], + sp->defMacAddr[0].mac_addr[3], + sp->defMacAddr[0].mac_addr[4], + sp->defMacAddr[0].mac_addr[5]); + + /* Set the factory defined MAC address initially */ + dev->addr_len = ETH_ALEN; + memcpy(dev->dev_addr, sp->defMacAddr, ETH_ALEN); + + /* Initialize the tasklet status flag */ + atomic_set(&(sp->tasklet_status), 0); + + + /* Initialize spinlocks */ + spin_lock_init(&sp->isr_lock); + spin_lock_init(&sp->tx_lock); + + /* SXE-002: Configure link and activity LED to init state + * on driver load. + */ + subid = sp->pdev->subsystem_device; + if ((subid & 0xFF) >= 0x07) { + val64 = readq(&bar0->gpio_control); + val64 |= 0x0000800000000000ULL; + writeq(val64, &bar0->gpio_control); + val64 = 0x0411040400000000ULL; + writeq(val64, (u64 *) ((u8 *) bar0 + 0x2700)); + val64 = readq(&bar0->gpio_control); + } + + /* Make Link state as off at this point, when the Link change + * interrupt comes the state will be automatically changed to + * the right state. + */ + netif_carrier_off(dev); + sp->last_link_state = LINK_DOWN; + + sp->rx_csum = 1; /* Rx chksum verify enabled by default */ + + return 0; + + set_swap_failed: + unregister_netdev(dev); + register_failed: + iounmap(sp->bar1); + bar1_remap_failed: + iounmap(sp->bar0); + bar0_remap_failed: + mem_alloc_failed: + freeSharedMem(sp); + init_failed: + pci_disable_device(pdev); + pci_release_regions(pdev); + pci_set_drvdata(pdev, NULL); + free_netdev(dev); + + return -ENODEV; +} + +/* +* Input Argument/s: +* pdev - structure containing the PCI related information of the device. +* Return value: +* void +* Description: +* This function is called by the Pci subsystem to release a PCI device +* and free up all resource held up by the device. This could be in response +* to a Hot plug event or when the driver is to be removed from memory. +*/ +static void __exit s2io_rem_nic(struct pci_dev *pdev) +{ + struct net_device *dev = + (struct net_device *) pci_get_drvdata(pdev); + nic_t *sp; + + if (dev == NULL) { + DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n"); + return; + } + sp = dev->priv; + freeSharedMem(sp); + iounmap(sp->bar0); + iounmap(sp->bar1); + pci_disable_device(pdev); + pci_release_regions(pdev); + pci_set_drvdata(pdev, NULL); + + unregister_netdev(dev); + + free_netdev(dev); +} + +int __init s2io_starter(void) +{ + return pci_module_init(&s2io_driver); +} + +void s2io_closer(void) +{ + pci_unregister_driver(&s2io_driver); + DBG_PRINT(INIT_DBG, "cleanup done\n"); +} + +module_init(s2io_starter); +module_exit(s2io_closer); diff -urN vanilla-linux/drivers/net/s2io/s2io.h vanilla-linux-patch/drivers/net/s2io/s2io.h --- vanilla-linux/drivers/net/s2io/s2io.h 1970-01-01 05:30:00.000000000 +0530 +++ vanilla-linux-patch/drivers/net/s2io/s2io.h 2004-03-19 11:22:44.000000000 +0530 @@ -0,0 +1,855 @@ +/************************************************************************ + * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC + * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com) + + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + * Drivers based on or derived from this code fall under the GPL and must + * retain the authorship, copyright and license notice. This file is not + * a complete program and may only be used when the entire operating + * system is licensed under the GPL. + * See the file COPYING in this distribution for more information. + ************************************************************************/ +#ifndef _S2IO_H +#define _S2IO_H + +#define TBD 0 +#define BIT(loc) (((u64)0x8000000000000000ULL) >> loc) +#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) + +#ifndef BOOL +#define BOOL int +#endif + +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif + +#undef SUCCESS +#define SUCCESS 0 +#define FAILURE -1 + +/* Maximum outstanding splits to be configured into xena. */ +typedef enum xena_max_outstanding_splits { + XENA_ONE_SPLIT_TRANSACTION = 0, + XENA_TWO_SPLIT_TRANSACTION = 1, + XENA_THREE_SPLIT_TRANSACTION = 2, + XENA_FOUR_SPLIT_TRANSACTION = 3, + XENA_EIGHT_SPLIT_TRANSACTION = 4, + XENA_TWELVE_SPLIT_TRANSACTION = 5, + XENA_SIXTEEN_SPLIT_TRANSACTION = 6, + XENA_THIRTYTWO_SPLIT_TRANSACTION = 7 +} xena_max_outstanding_splits; +#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) + +/* OS concerned variables and constants */ +#define WATCH_DOG_TIMEOUT 5*HZ +#define EFILL 0x1234 +#define ALIGN_SIZE 127 +#define PCIX_COMMAND_REGISTER 0x62 + +/* + * Debug related variables. + */ +#define DEBUG_ON TRUE + +/* different debug levels. */ +#define ERR_DBG 0 +#define INIT_DBG 1 +#define INFO_DBG 2 +#define TX_DBG 3 +#define INTR_DBG 4 + +/* Global variable that defines the present debug level of the driver. */ +int debug_level = ERR_DBG; /* Default level. */ + +/* DEBUG message print. */ +#define DBG_PRINT(dbg_level, args...) if(!(debug_level> 16) & 0xFFFF) +#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) + + u64 Control_2; +#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) +#define SET_BUFFER0_SIZE(val) vBIT(val,0,16) +#define MASK_VLAN_TAG vBIT(0xFFFF,48,16) +#define SET_VLAN_TAG(val) vBIT(val,48,16) +#define SET_NUM_TAG(val) vBIT(val,16,32) + +#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16))) +/* +#define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31)) +#define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47)) +*/ + u64 Buffer0_ptr; +} RxD_t; + + +/* Structure that represents the Rx descriptor block which contains + * 128 Rx descriptors. + */ +typedef struct _RxD_block { +#define MAX_RXDS_PER_BLOCK 127 + RxD_t rxd[MAX_RXDS_PER_BLOCK]; + + u64 reserved_0; +#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFF + u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */ + u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */ + u64 pNext_RxD_Blk_physical; /* Buff0_ptr. + In a 32 bit arch the upper 32 bits + should be 0 */ +} RxD_block_t; + +/* Structure which stores all the MAC control parameters */ + +/* This structure stores the offset of the RxD in the ring + * from which the Rx Interrupt processor can start picking + * up the RxDs for processing. + */ +typedef struct _rx_curr_get_info_t { + u32 block_index; + u32 offset; + u32 ring_len; +} rx_curr_get_info_t; + +typedef rx_curr_get_info_t rx_curr_put_info_t; + +/* This structure stores the offset of the TxDl in the FIFO + * from which the Tx Interrupt processor can start picking + * up the TxDLs for send complete interrupt processing. + */ +typedef struct { + u32 offset; + u32 fifo_len; +} tx_curr_get_info_t; + +typedef tx_curr_get_info_t tx_curr_put_info_t; + +/* Infomation related to the Tx and Rx FIFOs and Rings of Xena + * is maintained in this structure. + */ +typedef struct mac_info { +/* rx side stuff */ + u32 rxd_ring_mem_sz; + RxD_t *RxRing[MAX_RX_RINGS]; /* Logical Rx ring pointers */ + dma_addr_t RxRing_Phy[MAX_RX_RINGS]; + + /* Put pointer info which indictes which RxD has to be replenished + * with a new buffer. + */ + rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS]; + + /* Get pointer info which indictes which is the last RxD that was + * processed by the driver. + */ + rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS]; + + u16 rmac_pause_time; + + /* this will be used in receive function, this decides which ring would + be processed first. eg: ring with priority value 0 (highest) should + be processed first. + first 3 LSB bits represent ring number which should be processed + first, similarly next 3 bits represent next ring to be processed. + eg: value of _rx_ring_pri_map = 0x0000 003A means + ring #2 would be processed first and #7 would be processed next + */ + u32 _rx_ring_pri_map; + +/* tx side stuff */ + void *txd_list_mem; /* orignal pointer to allocated mem */ + dma_addr_t txd_list_mem_phy; + u32 txd_list_mem_sz; + + /* logical pointer of start of each Tx FIFO */ + TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS]; + + /* logical pointer of start of TxDL which corresponds to each Tx FIFO */ + TxD_t *txdl_start[MAX_TX_FIFOS]; + + /* Same as txdl_start but phy addr */ + dma_addr_t txdl_start_phy[MAX_TX_FIFOS]; + +/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/ + tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS]; + tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS]; + + u16 txdl_len; /* length of a TxDL, same for all */ + + void *stats_mem; /* orignal pointer to allocated mem */ + dma_addr_t stats_mem_phy; /* Physical address of the stat block */ + u32 stats_mem_sz; + StatInfo_t *StatsInfo; /* Logical address of the stat block */ +} mac_info_t; + +/* structure representing the user defined MAC addresses */ +typedef struct { + char addr[ETH_ALEN]; + int usage_cnt; +} usr_addr_t; + +/* Structure that holds the Phy and virt addresses of the Blocks */ +typedef struct rx_block_info { + RxD_t *block_virt_addr; + dma_addr_t block_dma_addr; +} rx_block_info_t; + +/* Structure representing one instance of the NIC */ +typedef struct s2io_nic { +#define MAX_MAC_SUPPORTED 16 +#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED + + macaddr_t defMacAddr[MAX_MAC_SUPPORTED]; + macaddr_t preMacAddr[MAX_MAC_SUPPORTED]; + + struct net_device_stats stats; + caddr_t bar0; + caddr_t bar1; + struct config_param config; + mac_info_t mac_control; + int high_dma_flag; + int device_close_flag; + int device_enabled_once; + + char name[32]; + struct tasklet_struct task; + atomic_t tasklet_status; + struct timer_list timer; + struct net_device *dev; + struct pci_dev *pdev; + + u16 vendor_id; + u16 device_id; + u16 ccmd; + u32 cbar0_1; + u32 cbar0_2; + u32 cbar1_1; + u32 cbar1_2; + u32 cirq; + u8 cache_line; + u32 rom_expansion; + u16 pcix_cmd; + u32 config_space[256 / sizeof(u32)]; + u32 irq; + atomic_t rx_bufs_left[MAX_RX_RINGS]; + + spinlock_t isr_lock; + spinlock_t tx_lock; + +#define PROMISC 1 +#define ALL_MULTI 2 + +#define MAX_ADDRS_SUPPORTED 64 + u16 usr_addr_count; + u16 mc_addr_count; + usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED]; + + u16 m_cast_flg; + u16 all_multi_pos; + u16 promisc_flg; + + u16 tx_pkt_count; + u16 rx_pkt_count; + u16 tx_err_count; + u16 rx_err_count; + +#if DEBUG_ON + u64 rxpkt_bytes; + u64 txpkt_bytes; + int int_cnt; + int rxint_cnt; + int txint_cnt; + u64 rxpkt_cnt; +#endif + + /* Place holders for the virtual and physical addresses of + * all the Rx Blocks + */ + struct rx_block_info + rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING]; + int block_count[MAX_RX_RINGS]; + int pkt_cnt[MAX_RX_RINGS]; + + /* Id timer, used to blink NIC to physically identify NIC. */ + struct timer_list id_timer; + + /* Restart timer, used to restart NIC if the device is stuck and + * a schedule task that will set the correct Link state once the + * NIC's PHY has stabilized after a state change. + */ +#ifdef INIT_TQUEUE + struct tq_struct rst_timer_task; + struct tq_struct set_link_task; +#else + struct work_struct rst_timer_task; + struct work_struct set_link_task; +#endif + + /* Flag that can be used to turn on or turn off the Rx checksum + * offload feature. + */ + int rx_csum; + + /* after blink, the adapter must be restored with original + * values. + */ + u64 adapt_ctrl_org; + + /* Last known link state. */ + u16 last_link_state; +#define LINK_DOWN 1 +#define LINK_UP 2 +} nic_t __cacheline_aligned; + +#define RESET_ERROR 1; +#define CMD_ERROR 2; + +/* Default Tunable parameters of the NIC. */ +#define DEFAULT_FIFO_LEN 4096 +#define SMALL_RXD_CNT 40 * (MAX_RXDS_PER_BLOCK+1) +#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1) + +/* OS related system calls */ +#ifndef readq +static inline u64 readq(void *addr) +{ + u64 ret = 0; + ret = readl(addr + 4); + (u64) ret <<= 32; + (u64) ret |= readl(addr); + + return ret; +} +#endif + +#ifndef writeq +static inline void writeq(u64 val, void *addr) +{ + writel((u32) (val), addr); + writel((u32) (val >> 32), (addr + 4)); +} +#endif + +/* Interrupt related values of Xena */ + +#define ENABLE_INTRS 1 +#define DISABLE_INTRS 2 + +/* Highest level interrupt blocks */ +#define TX_PIC_INTR (0x0001<<0) +#define TX_DMA_INTR (0x0001<<1) +#define TX_MAC_INTR (0x0001<<2) +#define TX_XGXS_INTR (0x0001<<3) +#define TX_TRAFFIC_INTR (0x0001<<4) +#define RX_PIC_INTR (0x0001<<5) +#define RX_DMA_INTR (0x0001<<6) +#define RX_MAC_INTR (0x0001<<7) +#define RX_XGXS_INTR (0x0001<<8) +#define RX_TRAFFIC_INTR (0x0001<<9) +#define MC_INTR (0x0001<<10) +#define ENA_ALL_INTRS ( TX_PIC_INTR | \ + TX_DMA_INTR | \ + TX_MAC_INTR | \ + TX_XGXS_INTR | \ + TX_TRAFFIC_INTR | \ + RX_PIC_INTR | \ + RX_DMA_INTR | \ + RX_MAC_INTR | \ + RX_XGXS_INTR | \ + RX_TRAFFIC_INTR | \ + MC_INTR ) + +/* Interrupt masks for the general interrupt mask register */ +#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL + +#define TXPIC_INT_M BIT(0) +#define TXDMA_INT_M BIT(1) +#define TXMAC_INT_M BIT(2) +#define TXXGXS_INT_M BIT(3) +#define TXTRAFFIC_INT_M BIT(8) +#define PIC_RX_INT_M BIT(32) +#define RXDMA_INT_M BIT(33) +#define RXMAC_INT_M BIT(34) +#define MC_INT_M BIT(35) +#define RXXGXS_INT_M BIT(36) +#define RXTRAFFIC_INT_M BIT(40) + +/* PIC level Interrupts TODO*/ + +/* DMA level Inressupts */ +#define TXDMA_PFC_INT_M BIT(0) + /* PFC block interrupts */ +#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */ + +/* + * Prototype declaration. + */ +static int __devinit s2io_init_nic(struct pci_dev *pdev, + const struct pci_device_id *pre); +static void __exit s2io_rem_nic(struct pci_dev *pdev); +static int initSharedMem(struct s2io_nic *sp); +static void freeSharedMem(struct s2io_nic *sp); +static int initNic(struct s2io_nic *nic); +#ifndef CONFIG_S2IO_NAPI +static void rxIntrHandler(struct s2io_nic *sp); +#endif +static void txIntrHandler(struct s2io_nic *sp); +static void alarmIntrHandler(struct s2io_nic *sp); + +static int s2io_starter(void); +void s2io_closer(void); +static void s2io_tx_watchdog(struct net_device *dev); +static void s2io_tasklet(unsigned long dev_addr); +static void s2io_set_multicast(struct net_device *dev); +static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no); +void s2io_link(nic_t * sp, int link); +void s2io_reset(nic_t * sp); +#ifdef CONFIG_S2IO_NAPI +static int s2io_poll(struct net_device *dev, int *budget); +#endif +static void s2io_init_pci(nic_t * sp); +int s2io_set_mac_addr(struct net_device *dev, u8 * addr); +static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs); +static int verify_xena_quiescence(u64 val64, int flag); +static struct ethtool_ops netdev_ethtool_ops; + +#endif /* _S2IO_H */ diff -urN vanilla-linux/drivers/net/tags vanilla-linux-patch/drivers/net/tags --- vanilla-linux/drivers/net/tags 2004-03-16 16:20:29.000000000 +0530 +++ vanilla-linux-patch/drivers/net/tags 1970-01-01 05:30:00.000000000 +0530 @@ -1,1958 +0,0 @@ -!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ -!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ -!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ -!_TAG_PROGRAM_NAME Exuberant Ctags // -!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ -!_TAG_PROGRAM_VERSION 5.4 // -ACPI_LENOFF_LEN_MASK tg3.h 351;" d -ACPI_LENOFF_LEN_SHIFT tg3.h 352;" d -ACPI_LENOFF_OFF_MASK tg3.h 353;" d -ACPI_LENOFF_OFF_SHIFT tg3.h 354;" d -ADVERTISE_PAUSE_ASYM tg3.h 1458;" d -ADVERTISE_PAUSE_CAP tg3.h 1455;" d -ANEG_CFG_ACK tg3.c 1504;" d file: -ANEG_CFG_FD tg3.c 1510;" d file: -ANEG_CFG_HD tg3.c 1509;" d file: -ANEG_CFG_INVAL tg3.c 1511;" d file: -ANEG_CFG_NP tg3.c 1503;" d file: -ANEG_CFG_PS1 tg3.c 1508;" d file: -ANEG_CFG_PS2 tg3.c 1507;" d file: -ANEG_CFG_RF1 tg3.c 1506;" d file: -ANEG_CFG_RF2 tg3.c 1505;" d file: -ANEG_DONE tg3.c 1515;" d file: -ANEG_FAILED tg3.c 1517;" d file: -ANEG_OK tg3.c 1514;" d file: -ANEG_STATE_ABILITY_DETECT tg3.c 1465;" d file: -ANEG_STATE_ABILITY_DETECT_INIT tg3.c 1464;" d file: -ANEG_STATE_ACK_DETECT tg3.c 1467;" d file: -ANEG_STATE_ACK_DETECT_INIT tg3.c 1466;" d file: -ANEG_STATE_AN_ENABLE tg3.c 1460;" d file: -ANEG_STATE_COMPLETE_ACK tg3.c 1469;" d file: -ANEG_STATE_COMPLETE_ACK_INIT tg3.c 1468;" d file: -ANEG_STATE_DISABLE_LINK_OK tg3.c 1463;" d file: -ANEG_STATE_IDLE_DETECT tg3.c 1471;" d file: -ANEG_STATE_IDLE_DETECT_INIT tg3.c 1470;" d file: -ANEG_STATE_LINK_OK tg3.c 1472;" d file: -ANEG_STATE_NEXT_PAGE_WAIT tg3.c 1474;" d file: -ANEG_STATE_NEXT_PAGE_WAIT_INIT tg3.c 1473;" d file: -ANEG_STATE_RESTART tg3.c 1462;" d file: -ANEG_STATE_RESTART_INIT tg3.c 1461;" d file: -ANEG_STATE_SETTLE_TIME tg3.c 1519;" d file: -ANEG_STATE_UNKNOWN tg3.c 1459;" d file: -ANEG_TIMER_ENAB tg3.c 1516;" d file: -ASIC_REV_5700 tg3.h 122;" d -ASIC_REV_5701 tg3.h 123;" d -ASIC_REV_5703 tg3.h 124;" d -ASIC_REV_5704 tg3.h 125;" d -ASIC_REV_5705 tg3.h 126;" d -AUTONEG_INVALID tg3.h 1793;" d -BDINFO_FLAGS_DISABLED tg3.h 18;" d -BDINFO_FLAGS_MAXLEN_MASK tg3.h 19;" d -BDINFO_FLAGS_MAXLEN_SHIFT tg3.h 20;" d -BDINFO_FLAGS_USE_EXT_RECV tg3.h 17;" d -BUFMGR_DMA_DESC_POOL_ADDR tg3.h 911;" d -BUFMGR_DMA_DESC_POOL_SIZE tg3.h 912;" d -BUFMGR_DMA_HIGH_WATER tg3.h 915;" d -BUFMGR_DMA_LOW_WATER tg3.h 913;" d -BUFMGR_HWDIAG_0 tg3.h 921;" d -BUFMGR_HWDIAG_1 tg3.h 922;" d -BUFMGR_HWDIAG_2 tg3.h 923;" d -BUFMGR_MB_ALLOC_BIT tg3.h 907;" d -BUFMGR_MB_HIGH_WATER tg3.h 902;" d -BUFMGR_MB_MACRX_LOW_WATER tg3.h 898;" d -BUFMGR_MB_POOL_ADDR tg3.h 892;" d -BUFMGR_MB_POOL_SIZE tg3.h 893;" d -BUFMGR_MB_RDMA_LOW_WATER tg3.h 894;" d -BUFMGR_MODE tg3.h 883;" d -BUFMGR_MODE_ATTN_ENABLE tg3.h 886;" d -BUFMGR_MODE_BM_TEST tg3.h 887;" d -BUFMGR_MODE_ENABLE tg3.h 885;" d -BUFMGR_MODE_MBLOW_ATTN_ENAB tg3.h 888;" d -BUFMGR_MODE_RESET tg3.h 884;" d -BUFMGR_RX_DMA_ALLOC_REQ tg3.h 917;" d -BUFMGR_RX_DMA_ALLOC_RESP tg3.h 918;" d -BUFMGR_RX_MB_ALLOC_REQ tg3.h 906;" d -BUFMGR_RX_MB_ALLOC_RESP tg3.h 908;" d -BUFMGR_STATUS tg3.h 889;" d -BUFMGR_STATUS_ERROR tg3.h 890;" d -BUFMGR_STATUS_MBLOW tg3.h 891;" d -BUFMGR_TX_DMA_ALLOC_REQ tg3.h 919;" d -BUFMGR_TX_DMA_ALLOC_RESP tg3.h 920;" d -BUFMGR_TX_MB_ALLOC_REQ tg3.h 909;" d -BUFMGR_TX_MB_ALLOC_RESP tg3.h 910;" d -CHIPREV_5700_AX tg3.h 128;" d -CHIPREV_5700_BX tg3.h 129;" d -CHIPREV_5700_CX tg3.h 130;" d -CHIPREV_5701_AX tg3.h 131;" d -CHIPREV_ID_5700_A0 tg3.h 101;" d -CHIPREV_ID_5700_A1 tg3.h 102;" d -CHIPREV_ID_5700_ALTIMA tg3.h 106;" d -CHIPREV_ID_5700_B0 tg3.h 103;" d -CHIPREV_ID_5700_B1 tg3.h 104;" d -CHIPREV_ID_5700_B3 tg3.h 105;" d -CHIPREV_ID_5700_C0 tg3.h 107;" d -CHIPREV_ID_5701_A0 tg3.h 108;" d -CHIPREV_ID_5701_B0 tg3.h 109;" d -CHIPREV_ID_5701_B2 tg3.h 110;" d -CHIPREV_ID_5701_B5 tg3.h 111;" d -CHIPREV_ID_5703_A0 tg3.h 112;" d -CHIPREV_ID_5703_A1 tg3.h 113;" d -CHIPREV_ID_5703_A2 tg3.h 114;" d -CHIPREV_ID_5703_A3 tg3.h 115;" d -CHIPREV_ID_5704_A0 tg3.h 116;" d -CHIPREV_ID_5704_A1 tg3.h 117;" d -CHIPREV_ID_5704_A2 tg3.h 118;" d -CHIPREV_ID_5705_A0 tg3.h 119;" d -CHIPREV_ID_5705_A1 tg3.h 120;" d -CLOCK_CTRL_44MHZ_CORE tg3.h 186;" d -CLOCK_CTRL_625_CORE tg3.h 187;" d -CLOCK_CTRL_ALTCLK tg3.h 184;" d -CLOCK_CTRL_CLKRUN_OENABLE tg3.h 189;" d -CLOCK_CTRL_CORECLK_DISABLE tg3.h 181;" d -CLOCK_CTRL_DELAY_PCI_GRANT tg3.h 190;" d -CLOCK_CTRL_FORCE_CLKRUN tg3.h 188;" d -CLOCK_CTRL_PWRDOWN_PLL133 tg3.h 185;" d -CLOCK_CTRL_RXCLK_DISABLE tg3.h 182;" d -CLOCK_CTRL_TXCLK_DISABLE tg3.h 183;" d -COS_out_packets tg3.h /^ tg3_stat64_t COS_out_packets[16];$/;" m struct:tg3_hw_stats -COS_rx_filter_dropped tg3.h /^ tg3_stat64_t COS_rx_filter_dropped;$/;" m struct:tg3_hw_stats -COS_rx_packets tg3.h /^ tg3_stat64_t COS_rx_packets[16];$/;" m struct:tg3_hw_stats -CPU_EVTMASK tg3.h 982;" d -CPU_HW_BP tg3.h 990;" d -CPU_INSN tg3.h 985;" d -CPU_LAST_BRANCH_ADDR tg3.h 993;" d -CPU_MODE tg3.h 978;" d -CPU_MODE_HALT tg3.h 980;" d -CPU_MODE_RESET tg3.h 979;" d -CPU_PC tg3.h 984;" d -CPU_R0 tg3.h 996;" d -CPU_R1 tg3.h 997;" d -CPU_R10 tg3.h 1006;" d -CPU_R11 tg3.h 1007;" d -CPU_R12 tg3.h 1008;" d -CPU_R13 tg3.h 1009;" d -CPU_R14 tg3.h 1010;" d -CPU_R15 tg3.h 1011;" d -CPU_R16 tg3.h 1012;" d -CPU_R17 tg3.h 1013;" d -CPU_R18 tg3.h 1014;" d -CPU_R19 tg3.h 1015;" d -CPU_R2 tg3.h 998;" d -CPU_R20 tg3.h 1016;" d -CPU_R21 tg3.h 1017;" d -CPU_R22 tg3.h 1018;" d -CPU_R23 tg3.h 1019;" d -CPU_R24 tg3.h 1020;" d -CPU_R25 tg3.h 1021;" d -CPU_R26 tg3.h 1022;" d -CPU_R27 tg3.h 1023;" d -CPU_R28 tg3.h 1024;" d -CPU_R29 tg3.h 1025;" d -CPU_R3 tg3.h 999;" d -CPU_R30 tg3.h 1026;" d -CPU_R31 tg3.h 1027;" d -CPU_R4 tg3.h 1000;" d -CPU_R5 tg3.h 1001;" d -CPU_R6 tg3.h 1002;" d -CPU_R7 tg3.h 1003;" d -CPU_R8 tg3.h 1004;" d -CPU_R9 tg3.h 1005;" d -CPU_SPAD_UFLOW tg3.h 986;" d -CPU_SPAD_UFLOW_SET tg3.h 994;" d -CPU_STATE tg3.h 981;" d -CPU_WDOG_CLEAR tg3.h 987;" d -CPU_WDOG_PC tg3.h 989;" d -CPU_WDOG_SAVED_STATE tg3.h 992;" d -CPU_WDOG_VECTOR tg3.h 988;" d -DEFAULT_DMA_HIGH_WATER tg3.h 916;" d -DEFAULT_DMA_LOW_WATER tg3.h 914;" d -DEFAULT_MB_HIGH_WATER tg3.h 903;" d -DEFAULT_MB_HIGH_WATER_5705 tg3.h 904;" d -DEFAULT_MB_HIGH_WATER_JUMBO tg3.h 905;" d -DEFAULT_MB_MACRX_LOW_WATER tg3.h 899;" d -DEFAULT_MB_MACRX_LOW_WATER_5705 tg3.h 900;" d -DEFAULT_MB_MACRX_LOW_WATER_JUMBO tg3.h 901;" d -DEFAULT_MB_RDMA_LOW_WATER tg3.h 895;" d -DEFAULT_MB_RDMA_LOW_WATER_5705 tg3.h 896;" d -DEFAULT_MB_RDMA_LOW_WATER_JUMBO tg3.h 897;" d -DEFAULT_RXCOAL_MAXF_INT tg3.h 823;" d -DEFAULT_RXCOAL_TICK_INT tg3.h 819;" d -DEFAULT_RXCOL_TICKS tg3.h 804;" d -DEFAULT_RXMAX_FRAMES tg3.h 812;" d -DEFAULT_STAT_COAL_TICKS tg3.h 827;" d -DEFAULT_TXCOAL_MAXF_INT tg3.h 825;" d -DEFAULT_TXCOAL_TICK_INT tg3.h 821;" d -DEFAULT_TXCOL_TICKS tg3.h 808;" d -DEFAULT_TXMAX_FRAMES tg3.h 816;" d -DMAC_MODE tg3.h 1186;" d -DMAC_MODE_ENABLE tg3.h 1188;" d -DMAC_MODE_RESET tg3.h 1187;" d -DMA_RWCTRL_ASSERT_ALL_BE tg3.h 165;" d -DMA_RWCTRL_MIN_DMA tg3.h 139;" d -DMA_RWCTRL_MIN_DMA_SHIFT tg3.h 140;" d -DMA_RWCTRL_ONE_DMA tg3.h 159;" d -DMA_RWCTRL_PCI_READ_CMD tg3.h 166;" d -DMA_RWCTRL_PCI_READ_CMD_SHIFT tg3.h 167;" d -DMA_RWCTRL_PCI_WRITE_CMD tg3.h 168;" d -DMA_RWCTRL_PCI_WRITE_CMD_SHIFT tg3.h 169;" d -DMA_RWCTRL_READ_BNDRY_1024 tg3.h 149;" d -DMA_RWCTRL_READ_BNDRY_128 tg3.h 146;" d -DMA_RWCTRL_READ_BNDRY_16 tg3.h 143;" d -DMA_RWCTRL_READ_BNDRY_256 tg3.h 147;" d -DMA_RWCTRL_READ_BNDRY_32 tg3.h 144;" d -DMA_RWCTRL_READ_BNDRY_512 tg3.h 148;" d -DMA_RWCTRL_READ_BNDRY_64 tg3.h 145;" d -DMA_RWCTRL_READ_BNDRY_DISAB tg3.h 142;" d -DMA_RWCTRL_READ_BNDRY_MASK tg3.h 141;" d -DMA_RWCTRL_READ_WATER tg3.h 160;" d -DMA_RWCTRL_READ_WATER_SHIFT tg3.h 161;" d -DMA_RWCTRL_USE_MEM_READ_MULT tg3.h 164;" d -DMA_RWCTRL_WRITE_BNDRY_1024 tg3.h 158;" d -DMA_RWCTRL_WRITE_BNDRY_128 tg3.h 155;" d -DMA_RWCTRL_WRITE_BNDRY_16 tg3.h 152;" d -DMA_RWCTRL_WRITE_BNDRY_256 tg3.h 156;" d -DMA_RWCTRL_WRITE_BNDRY_32 tg3.h 153;" d -DMA_RWCTRL_WRITE_BNDRY_512 tg3.h 157;" d -DMA_RWCTRL_WRITE_BNDRY_64 tg3.h 154;" d -DMA_RWCTRL_WRITE_BNDRY_DISAB tg3.h 151;" d -DMA_RWCTRL_WRITE_BNDRY_MASK tg3.h 150;" d -DMA_RWCTRL_WRITE_WATER tg3.h 162;" d -DMA_RWCTRL_WRITE_WATER_SHIFT tg3.h 163;" d -DRV_MODULE_NAME tg3.c 57;" d file: -DRV_MODULE_RELDATE tg3.c 60;" d file: -DRV_MODULE_VERSION tg3.c 59;" d file: -DRV_STATE_START tg3.h 1385;" d -DRV_STATE_SUSPEND tg3.h 1388;" d -DRV_STATE_UNLOAD tg3.h 1386;" d -DRV_STATE_WOL tg3.h 1387;" d -DUPLEX_INVALID tg3.h 1792;" d -EEPROM_ADDR_ADDR_MASK tg3.h 1278;" d -EEPROM_ADDR_ADDR_SHIFT tg3.h 1279;" d -EEPROM_ADDR_CLKPERD_SHIFT tg3.h 1277;" d -EEPROM_ADDR_COMPLETE tg3.h 1272;" d -EEPROM_ADDR_DEVID_MASK tg3.h 1274;" d -EEPROM_ADDR_DEVID_SHIFT tg3.h 1275;" d -EEPROM_ADDR_FSM_RESET tg3.h 1273;" d -EEPROM_ADDR_READ tg3.h 1271;" d -EEPROM_ADDR_START tg3.h 1276;" d -EEPROM_ADDR_WRITE tg3.h 1270;" d -EEPROM_CHIP_SIZE tg3.h 1281;" d -EEPROM_DEFAULT_CLOCK_PERIOD tg3.h 1280;" d -FTQ_DMA_COMP_DISC_CTL tg3.h 1115;" d -FTQ_DMA_COMP_DISC_FIFO_ENQDEQ tg3.h 1117;" d -FTQ_DMA_COMP_DISC_FULL_CNT tg3.h 1116;" d -FTQ_DMA_COMP_DISC_WRITE_PEEK tg3.h 1118;" d -FTQ_DMA_HIGH_READ_CTL tg3.h 1111;" d -FTQ_DMA_HIGH_READ_FIFO_ENQDEQ tg3.h 1113;" d -FTQ_DMA_HIGH_READ_FULL_CNT tg3.h 1112;" d -FTQ_DMA_HIGH_READ_WRITE_PEEK tg3.h 1114;" d -FTQ_DMA_HIGH_WRITE_CTL tg3.h 1131;" d -FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ tg3.h 1133;" d -FTQ_DMA_HIGH_WRITE_FULL_CNT tg3.h 1132;" d -FTQ_DMA_HIGH_WRITE_WRITE_PEEK tg3.h 1134;" d -FTQ_DMA_NORM_READ_CTL tg3.h 1107;" d -FTQ_DMA_NORM_READ_FIFO_ENQDEQ tg3.h 1109;" d -FTQ_DMA_NORM_READ_FULL_CNT tg3.h 1108;" d -FTQ_DMA_NORM_READ_WRITE_PEEK tg3.h 1110;" d -FTQ_DMA_NORM_WRITE_CTL tg3.h 1127;" d -FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ tg3.h 1129;" d -FTQ_DMA_NORM_WRITE_FULL_CNT tg3.h 1128;" d -FTQ_DMA_NORM_WRITE_WRITE_PEEK tg3.h 1130;" d -FTQ_HOST_COAL_CTL tg3.h 1143;" d -FTQ_HOST_COAL_FIFO_ENQDEQ tg3.h 1145;" d -FTQ_HOST_COAL_FULL_CNT tg3.h 1144;" d -FTQ_HOST_COAL_WRITE_PEEK tg3.h 1146;" d -FTQ_MAC_TX_CTL tg3.h 1147;" d -FTQ_MAC_TX_FIFO_ENQDEQ tg3.h 1149;" d -FTQ_MAC_TX_FULL_CNT tg3.h 1148;" d -FTQ_MAC_TX_WRITE_PEEK tg3.h 1150;" d -FTQ_MB_FREE_CTL tg3.h 1151;" d -FTQ_MB_FREE_FIFO_ENQDEQ tg3.h 1153;" d -FTQ_MB_FREE_FULL_CNT tg3.h 1152;" d -FTQ_MB_FREE_WRITE_PEEK tg3.h 1154;" d -FTQ_RCVBD_COMP_CTL tg3.h 1155;" d -FTQ_RCVBD_COMP_FIFO_ENQDEQ tg3.h 1157;" d -FTQ_RCVBD_COMP_FULL_CNT tg3.h 1156;" d -FTQ_RCVBD_COMP_WRITE_PEEK tg3.h 1158;" d -FTQ_RCVDATA_COMP_CTL tg3.h 1167;" d -FTQ_RCVDATA_COMP_FIFO_ENQDEQ tg3.h 1169;" d -FTQ_RCVDATA_COMP_FULL_CNT tg3.h 1168;" d -FTQ_RCVDATA_COMP_WRITE_PEEK tg3.h 1170;" d -FTQ_RCVDATA_INI_CTL tg3.h 1163;" d -FTQ_RCVDATA_INI_FIFO_ENQDEQ tg3.h 1165;" d -FTQ_RCVDATA_INI_FULL_CNT tg3.h 1164;" d -FTQ_RCVDATA_INI_WRITE_PEEK tg3.h 1166;" d -FTQ_RCVLST_PLMT_CTL tg3.h 1159;" d -FTQ_RCVLST_PLMT_FIFO_ENQDEQ tg3.h 1161;" d -FTQ_RCVLST_PLMT_FULL_CNT tg3.h 1160;" d -FTQ_RCVLST_PLMT_WRITE_PEEK tg3.h 1162;" d -FTQ_RESET tg3.h 1105;" d -FTQ_SEND_BD_COMP_CTL tg3.h 1119;" d -FTQ_SEND_BD_COMP_FIFO_ENQDEQ tg3.h 1121;" d -FTQ_SEND_BD_COMP_FULL_CNT tg3.h 1120;" d -FTQ_SEND_BD_COMP_WRITE_PEEK tg3.h 1122;" d -FTQ_SEND_DATA_COMP_CTL tg3.h 1139;" d -FTQ_SEND_DATA_COMP_FIFO_ENQDEQ tg3.h 1141;" d -FTQ_SEND_DATA_COMP_FULL_CNT tg3.h 1140;" d -FTQ_SEND_DATA_COMP_WRITE_PEEK tg3.h 1142;" d -FTQ_SEND_DATA_INIT_CTL tg3.h 1123;" d -FTQ_SEND_DATA_INIT_FIFO_ENQDEQ tg3.h 1125;" d -FTQ_SEND_DATA_INIT_FULL_CNT tg3.h 1124;" d -FTQ_SEND_DATA_INIT_WRITE_PEEK tg3.h 1126;" d -FTQ_SWTYPE1_CTL tg3.h 1135;" d -FTQ_SWTYPE1_FIFO_ENQDEQ tg3.h 1137;" d -FTQ_SWTYPE1_FULL_CNT tg3.h 1136;" d -FTQ_SWTYPE1_WRITE_PEEK tg3.h 1138;" d -FTQ_SWTYPE2_CTL tg3.h 1171;" d -FTQ_SWTYPE2_FIFO_ENQDEQ tg3.h 1173;" d -FTQ_SWTYPE2_FULL_CNT tg3.h 1172;" d -FTQ_SWTYPE2_WRITE_PEEK tg3.h 1174;" d -FWCMD_NICDRV_ALIVE tg3.h 1375;" d -FWCMD_NICDRV_FIX_DMAR tg3.h 1379;" d -FWCMD_NICDRV_FIX_DMAW tg3.h 1380;" d -FWCMD_NICDRV_IPV4ADDR_CHG tg3.h 1377;" d -FWCMD_NICDRV_IPV6ADDR_CHG tg3.h 1378;" d -FWCMD_NICDRV_PAUSE_FW tg3.h 1376;" d -GET_ASIC_REV tg3.h 121;" d -GET_CHIP_REV tg3.h 127;" d -GET_CHIP_REV_ID tg3.h 98;" d -GET_METAL_REV tg3.h 132;" d -GET_REG32_1 tg3.c 5850;" d file: -GET_REG32_1 tg3.c 5889;" d file: -GET_REG32_LOOP tg3.c 5845;" d file: -GET_REG32_LOOP tg3.c 5888;" d file: -GRCMBOX_GENERAL_0 tg3.h 1038;" d -GRCMBOX_GENERAL_1 tg3.h 1039;" d -GRCMBOX_GENERAL_2 tg3.h 1040;" d -GRCMBOX_GENERAL_3 tg3.h 1041;" d -GRCMBOX_GENERAL_4 tg3.h 1042;" d -GRCMBOX_GENERAL_5 tg3.h 1043;" d -GRCMBOX_GENERAL_6 tg3.h 1044;" d -GRCMBOX_GENERAL_7 tg3.h 1045;" d -GRCMBOX_HIGH_PRIO_EV_MASK tg3.h 1099;" d -GRCMBOX_HIGH_PRIO_EV_VECTOR tg3.h 1098;" d -GRCMBOX_INTERRUPT_0 tg3.h 1034;" d -GRCMBOX_INTERRUPT_1 tg3.h 1035;" d -GRCMBOX_INTERRUPT_2 tg3.h 1036;" d -GRCMBOX_INTERRUPT_3 tg3.h 1037;" d -GRCMBOX_LOW_PRIO_EV_MASK tg3.h 1101;" d -GRCMBOX_LOW_PRIO_EV_VEC tg3.h 1100;" d -GRCMBOX_RCVJUMBO_PROD_IDX tg3.h 1048;" d -GRCMBOX_RCVMINI_PROD_IDX tg3.h 1049;" d -GRCMBOX_RCVRET_CON_IDX_0 tg3.h 1050;" d -GRCMBOX_RCVRET_CON_IDX_1 tg3.h 1051;" d -GRCMBOX_RCVRET_CON_IDX_10 tg3.h 1060;" d -GRCMBOX_RCVRET_CON_IDX_11 tg3.h 1061;" d -GRCMBOX_RCVRET_CON_IDX_12 tg3.h 1062;" d -GRCMBOX_RCVRET_CON_IDX_13 tg3.h 1063;" d -GRCMBOX_RCVRET_CON_IDX_14 tg3.h 1064;" d -GRCMBOX_RCVRET_CON_IDX_15 tg3.h 1065;" d -GRCMBOX_RCVRET_CON_IDX_2 tg3.h 1052;" d -GRCMBOX_RCVRET_CON_IDX_3 tg3.h 1053;" d -GRCMBOX_RCVRET_CON_IDX_4 tg3.h 1054;" d -GRCMBOX_RCVRET_CON_IDX_5 tg3.h 1055;" d -GRCMBOX_RCVRET_CON_IDX_6 tg3.h 1056;" d -GRCMBOX_RCVRET_CON_IDX_7 tg3.h 1057;" d -GRCMBOX_RCVRET_CON_IDX_8 tg3.h 1058;" d -GRCMBOX_RCVRET_CON_IDX_9 tg3.h 1059;" d -GRCMBOX_RCVSTD_PROD_IDX tg3.h 1047;" d -GRCMBOX_RELOAD_STAT tg3.h 1046;" d -GRCMBOX_SNDHOST_PROD_IDX_0 tg3.h 1066;" d -GRCMBOX_SNDHOST_PROD_IDX_1 tg3.h 1067;" d -GRCMBOX_SNDHOST_PROD_IDX_10 tg3.h 1076;" d -GRCMBOX_SNDHOST_PROD_IDX_11 tg3.h 1077;" d -GRCMBOX_SNDHOST_PROD_IDX_12 tg3.h 1078;" d -GRCMBOX_SNDHOST_PROD_IDX_13 tg3.h 1079;" d -GRCMBOX_SNDHOST_PROD_IDX_14 tg3.h 1080;" d -GRCMBOX_SNDHOST_PROD_IDX_15 tg3.h 1081;" d -GRCMBOX_SNDHOST_PROD_IDX_2 tg3.h 1068;" d -GRCMBOX_SNDHOST_PROD_IDX_3 tg3.h 1069;" d -GRCMBOX_SNDHOST_PROD_IDX_4 tg3.h 1070;" d -GRCMBOX_SNDHOST_PROD_IDX_5 tg3.h 1071;" d -GRCMBOX_SNDHOST_PROD_IDX_6 tg3.h 1072;" d -GRCMBOX_SNDHOST_PROD_IDX_7 tg3.h 1073;" d -GRCMBOX_SNDHOST_PROD_IDX_8 tg3.h 1074;" d -GRCMBOX_SNDHOST_PROD_IDX_9 tg3.h 1075;" d -GRCMBOX_SNDNIC_PROD_IDX_0 tg3.h 1082;" d -GRCMBOX_SNDNIC_PROD_IDX_1 tg3.h 1083;" d -GRCMBOX_SNDNIC_PROD_IDX_10 tg3.h 1092;" d -GRCMBOX_SNDNIC_PROD_IDX_11 tg3.h 1093;" d -GRCMBOX_SNDNIC_PROD_IDX_12 tg3.h 1094;" d -GRCMBOX_SNDNIC_PROD_IDX_13 tg3.h 1095;" d -GRCMBOX_SNDNIC_PROD_IDX_14 tg3.h 1096;" d -GRCMBOX_SNDNIC_PROD_IDX_15 tg3.h 1097;" d -GRCMBOX_SNDNIC_PROD_IDX_2 tg3.h 1084;" d -GRCMBOX_SNDNIC_PROD_IDX_3 tg3.h 1085;" d -GRCMBOX_SNDNIC_PROD_IDX_4 tg3.h 1086;" d -GRCMBOX_SNDNIC_PROD_IDX_5 tg3.h 1087;" d -GRCMBOX_SNDNIC_PROD_IDX_6 tg3.h 1088;" d -GRCMBOX_SNDNIC_PROD_IDX_7 tg3.h 1089;" d -GRCMBOX_SNDNIC_PROD_IDX_8 tg3.h 1090;" d -GRCMBOX_SNDNIC_PROD_IDX_9 tg3.h 1091;" d -GRC_EEPROM_ADDR tg3.h 1269;" d -GRC_EEPROM_CTRL tg3.h 1283;" d -GRC_EEPROM_DATA tg3.h 1282;" d -GRC_LCLCTRL_AUTO_SEEPROM tg3.h 1258;" d -GRC_LCLCTRL_BANK_SELECT tg3.h 1256;" d -GRC_LCLCTRL_CLEARINT tg3.h 1235;" d -GRC_LCLCTRL_EXTMEM_ENABLE tg3.h 1247;" d -GRC_LCLCTRL_GPIO_INPUT0 tg3.h 1238;" d -GRC_LCLCTRL_GPIO_INPUT1 tg3.h 1239;" d -GRC_LCLCTRL_GPIO_INPUT2 tg3.h 1240;" d -GRC_LCLCTRL_GPIO_OE0 tg3.h 1241;" d -GRC_LCLCTRL_GPIO_OE1 tg3.h 1242;" d -GRC_LCLCTRL_GPIO_OE2 tg3.h 1243;" d -GRC_LCLCTRL_GPIO_OUTPUT0 tg3.h 1244;" d -GRC_LCLCTRL_GPIO_OUTPUT1 tg3.h 1245;" d -GRC_LCLCTRL_GPIO_OUTPUT2 tg3.h 1246;" d -GRC_LCLCTRL_INT_ACTIVE tg3.h 1234;" d -GRC_LCLCTRL_INT_ON_ATTN tg3.h 1237;" d -GRC_LCLCTRL_MEMSZ_16M tg3.h 1255;" d -GRC_LCLCTRL_MEMSZ_1M tg3.h 1251;" d -GRC_LCLCTRL_MEMSZ_256K tg3.h 1249;" d -GRC_LCLCTRL_MEMSZ_2M tg3.h 1252;" d -GRC_LCLCTRL_MEMSZ_4M tg3.h 1253;" d -GRC_LCLCTRL_MEMSZ_512K tg3.h 1250;" d -GRC_LCLCTRL_MEMSZ_8M tg3.h 1254;" d -GRC_LCLCTRL_MEMSZ_MASK tg3.h 1248;" d -GRC_LCLCTRL_SETINT tg3.h 1236;" d -GRC_LCLCTRL_SSRAM_TYPE tg3.h 1257;" d -GRC_LOCAL_CTRL tg3.h 1233;" d -GRC_MDI_CTRL tg3.h 1284;" d -GRC_MEM_POWER_UP tg3.h 1268;" d -GRC_MISC_CFG tg3.h 1216;" d -GRC_MISC_CFG_BOARD_ID_5700 tg3.h 1221;" d -GRC_MISC_CFG_BOARD_ID_5701 tg3.h 1222;" d -GRC_MISC_CFG_BOARD_ID_5702FE tg3.h 1223;" d -GRC_MISC_CFG_BOARD_ID_5703 tg3.h 1224;" d -GRC_MISC_CFG_BOARD_ID_5703S tg3.h 1225;" d -GRC_MISC_CFG_BOARD_ID_5704 tg3.h 1226;" d -GRC_MISC_CFG_BOARD_ID_5704CIOBE tg3.h 1227;" d -GRC_MISC_CFG_BOARD_ID_5704_A2 tg3.h 1228;" d -GRC_MISC_CFG_BOARD_ID_5788 tg3.h 1229;" d -GRC_MISC_CFG_BOARD_ID_5788M tg3.h 1230;" d -GRC_MISC_CFG_BOARD_ID_AC91002A1 tg3.h 1231;" d -GRC_MISC_CFG_BOARD_ID_MASK tg3.h 1220;" d -GRC_MISC_CFG_CORECLK_RESET tg3.h 1217;" d -GRC_MISC_CFG_KEEP_GPHY_POWER tg3.h 1232;" d -GRC_MISC_CFG_PRESCALAR_MASK tg3.h 1218;" d -GRC_MISC_CFG_PRESCALAR_SHIFT tg3.h 1219;" d -GRC_MODE tg3.h 1192;" d -GRC_MODE_4X_NIC_SEND_RINGS tg3.h 1214;" d -GRC_MODE_ALLOW_BAD_FRMS tg3.h 1201;" d -GRC_MODE_BSWAP_DATA tg3.h 1196;" d -GRC_MODE_BSWAP_NONFRM_DATA tg3.h 1194;" d -GRC_MODE_FORCE_PCI32BIT tg3.h 1204;" d -GRC_MODE_HOST_SENDBDS tg3.h 1206;" d -GRC_MODE_HOST_STACKUP tg3.h 1205;" d -GRC_MODE_INCL_CRC tg3.h 1200;" d -GRC_MODE_IRQ_ON_DMA_ATTN tg3.h 1212;" d -GRC_MODE_IRQ_ON_FLOW_ATTN tg3.h 1213;" d -GRC_MODE_IRQ_ON_MAC_ATTN tg3.h 1211;" d -GRC_MODE_IRQ_ON_RX_CPU_ATTN tg3.h 1210;" d -GRC_MODE_IRQ_ON_TX_CPU_ATTN tg3.h 1209;" d -GRC_MODE_MCAST_FRM_ENABLE tg3.h 1215;" d -GRC_MODE_NOFRM_CRACKING tg3.h 1199;" d -GRC_MODE_NOIRQ_ON_RCV tg3.h 1203;" d -GRC_MODE_NOIRQ_ON_SENDS tg3.h 1202;" d -GRC_MODE_NO_RX_PHDR_CSUM tg3.h 1208;" d -GRC_MODE_NO_TX_PHDR_CSUM tg3.h 1207;" d -GRC_MODE_SPLITHDR tg3.h 1198;" d -GRC_MODE_UPD_ON_COAL tg3.h 1193;" d -GRC_MODE_WSWAP_DATA tg3.h 1197;" d -GRC_MODE_WSWAP_NONFRM_DATA tg3.h 1195;" d -GRC_REMOTE_RX_CPU_ATTN tg3.h 1263;" d -GRC_REMOTE_TX_CPU_ATTN tg3.h 1267;" d -GRC_RX_CPU_EVENT tg3.h 1260;" d -GRC_RX_CPU_SEM tg3.h 1262;" d -GRC_RX_TIMER_REF tg3.h 1261;" d -GRC_SEEPROM_DELAY tg3.h 1285;" d -GRC_TIMER tg3.h 1259;" d -GRC_TX_CPU_EVENT tg3.h 1264;" d -GRC_TX_CPU_SEM tg3.h 1266;" d -GRC_TX_TIMER_REF tg3.h 1265;" d -HIGH_RXCOL_TICKS tg3.h 805;" d -HIGH_RXMAX_FRAMES tg3.h 813;" d -HIGH_TXCOL_TICKS tg3.h 809;" d -HIGH_TXMAX_FRAMES tg3.h 817;" d -HOSTCC_FLOW_ATTN tg3.h 833;" d -HOSTCC_JUMBO_CON_IDX tg3.h 835;" d -HOSTCC_MINI_CON_IDX tg3.h 837;" d -HOSTCC_MODE tg3.h 788;" d -HOSTCC_MODE_32BYTE tg3.h 795;" d -HOSTCC_MODE_64BYTE tg3.h 794;" d -HOSTCC_MODE_ATTN tg3.h 791;" d -HOSTCC_MODE_CLRTICK_RXBD tg3.h 796;" d -HOSTCC_MODE_CLRTICK_TXBD tg3.h 797;" d -HOSTCC_MODE_ENABLE tg3.h 790;" d -HOSTCC_MODE_FULL_STATUS tg3.h 793;" d -HOSTCC_MODE_NOINT_ON_FORCE tg3.h 799;" d -HOSTCC_MODE_NOINT_ON_NOW tg3.h 798;" d -HOSTCC_MODE_NOW tg3.h 792;" d -HOSTCC_MODE_RESET tg3.h 789;" d -HOSTCC_RET_PROD_IDX_0 tg3.h 839;" d -HOSTCC_RET_PROD_IDX_1 tg3.h 840;" d -HOSTCC_RET_PROD_IDX_10 tg3.h 849;" d -HOSTCC_RET_PROD_IDX_11 tg3.h 850;" d -HOSTCC_RET_PROD_IDX_12 tg3.h 851;" d -HOSTCC_RET_PROD_IDX_13 tg3.h 852;" d -HOSTCC_RET_PROD_IDX_14 tg3.h 853;" d -HOSTCC_RET_PROD_IDX_15 tg3.h 854;" d -HOSTCC_RET_PROD_IDX_2 tg3.h 841;" d -HOSTCC_RET_PROD_IDX_3 tg3.h 842;" d -HOSTCC_RET_PROD_IDX_4 tg3.h 843;" d -HOSTCC_RET_PROD_IDX_5 tg3.h 844;" d -HOSTCC_RET_PROD_IDX_6 tg3.h 845;" d -HOSTCC_RET_PROD_IDX_7 tg3.h 846;" d -HOSTCC_RET_PROD_IDX_8 tg3.h 847;" d -HOSTCC_RET_PROD_IDX_9 tg3.h 848;" d -HOSTCC_RXCOAL_MAXF_INT tg3.h 822;" d -HOSTCC_RXCOAL_TICK_INT tg3.h 818;" d -HOSTCC_RXCOL_TICKS tg3.h 802;" d -HOSTCC_RXMAX_FRAMES tg3.h 810;" d -HOSTCC_SND_CON_IDX_0 tg3.h 855;" d -HOSTCC_SND_CON_IDX_1 tg3.h 856;" d -HOSTCC_SND_CON_IDX_10 tg3.h 865;" d -HOSTCC_SND_CON_IDX_11 tg3.h 866;" d -HOSTCC_SND_CON_IDX_12 tg3.h 867;" d -HOSTCC_SND_CON_IDX_13 tg3.h 868;" d -HOSTCC_SND_CON_IDX_14 tg3.h 869;" d -HOSTCC_SND_CON_IDX_15 tg3.h 870;" d -HOSTCC_SND_CON_IDX_2 tg3.h 857;" d -HOSTCC_SND_CON_IDX_3 tg3.h 858;" d -HOSTCC_SND_CON_IDX_4 tg3.h 859;" d -HOSTCC_SND_CON_IDX_5 tg3.h 860;" d -HOSTCC_SND_CON_IDX_6 tg3.h 861;" d -HOSTCC_SND_CON_IDX_7 tg3.h 862;" d -HOSTCC_SND_CON_IDX_8 tg3.h 863;" d -HOSTCC_SND_CON_IDX_9 tg3.h 864;" d -HOSTCC_STATS_BLK_HOST_ADDR tg3.h 829;" d -HOSTCC_STATS_BLK_NIC_ADDR tg3.h 831;" d -HOSTCC_STATUS tg3.h 800;" d -HOSTCC_STATUS_BLK_HOST_ADDR tg3.h 830;" d -HOSTCC_STATUS_BLK_NIC_ADDR tg3.h 832;" d -HOSTCC_STATUS_ERROR_ATTN tg3.h 801;" d -HOSTCC_STAT_COAL_TICKS tg3.h 826;" d -HOSTCC_STD_CON_IDX tg3.h 836;" d -HOSTCC_TXCOAL_MAXF_INT tg3.h 824;" d -HOSTCC_TXCOAL_TICK_INT tg3.h 820;" d -HOSTCC_TXCOL_TICKS tg3.h 806;" d -HOSTCC_TXMAX_FRAMES tg3.h 814;" d -KNOWN_PHY_ID tg3.h 1987;" d -LED_CTRL_1000MBPS_ON tg3.h 324;" d -LED_CTRL_1000MBPS_STATUS tg3.h 330;" d -LED_CTRL_100MBPS_ON tg3.h 325;" d -LED_CTRL_100MBPS_STATUS tg3.h 331;" d -LED_CTRL_10MBPS_ON tg3.h 326;" d -LED_CTRL_10MBPS_STATUS tg3.h 332;" d -LED_CTRL_BLINK_PER_OVERRIDE tg3.h 339;" d -LED_CTRL_BLINK_RATE_MASK tg3.h 337;" d -LED_CTRL_BLINK_RATE_OVERRIDE tg3.h 340;" d -LED_CTRL_BLINK_RATE_SHIFT tg3.h 338;" d -LED_CTRL_LNKLED_OVERRIDE tg3.h 323;" d -LED_CTRL_MAC_MODE tg3.h 334;" d -LED_CTRL_PHY_MODE_1 tg3.h 335;" d -LED_CTRL_PHY_MODE_2 tg3.h 336;" d -LED_CTRL_TRAFFIC_BLINK tg3.h 328;" d -LED_CTRL_TRAFFIC_LED tg3.h 329;" d -LED_CTRL_TRAFFIC_OVERRIDE tg3.h 327;" d -LED_CTRL_TRAFFIC_STATUS tg3.h 333;" d -LOW_RXCOL_TICKS tg3.h 803;" d -LOW_RXMAX_FRAMES tg3.h 811;" d -LOW_TXCOL_TICKS tg3.h 807;" d -LOW_TXMAX_FRAMES tg3.h 815;" d -LPA_PAUSE_ASYM tg3.h 1464;" d -LPA_PAUSE_CAP tg3.h 1461;" d -MAC_ACPI_LEN_OFFSET tg3.h 350;" d -MAC_ACPI_MBUF_PTR tg3.h 349;" d -MAC_ADDR_0_HIGH tg3.h 341;" d -MAC_ADDR_0_LOW tg3.h 342;" d -MAC_ADDR_1_HIGH tg3.h 343;" d -MAC_ADDR_1_LOW tg3.h 344;" d -MAC_ADDR_2_HIGH tg3.h 345;" d -MAC_ADDR_2_LOW tg3.h 346;" d -MAC_ADDR_3_HIGH tg3.h 347;" d -MAC_ADDR_3_LOW tg3.h 348;" d -MAC_AUTO_POLL_ERROR tg3.h 390;" d -MAC_AUTO_POLL_STATUS tg3.h 389;" d -MAC_EVENT tg3.h 313;" d -MAC_EVENT_AP_ERROR tg3.h 318;" d -MAC_EVENT_LNKSTATE_CHANGED tg3.h 315;" d -MAC_EVENT_MI_COMPLETION tg3.h 316;" d -MAC_EVENT_MI_INTERRUPT tg3.h 317;" d -MAC_EVENT_ODI_ERROR tg3.h 319;" d -MAC_EVENT_PORT_DECODE_ERR tg3.h 314;" d -MAC_EVENT_RXSTAT_OVERRUN tg3.h 320;" d -MAC_EVENT_TXSTAT_OVERRUN tg3.h 321;" d -MAC_EXTADDR_0_HIGH tg3.h 472;" d -MAC_EXTADDR_0_LOW tg3.h 473;" d -MAC_EXTADDR_10_HIGH tg3.h 492;" d -MAC_EXTADDR_10_LOW tg3.h 493;" d -MAC_EXTADDR_11_HIGH tg3.h 494;" d -MAC_EXTADDR_11_LOW tg3.h 495;" d -MAC_EXTADDR_1_HIGH tg3.h 474;" d -MAC_EXTADDR_1_LOW tg3.h 475;" d -MAC_EXTADDR_2_HIGH tg3.h 476;" d -MAC_EXTADDR_2_LOW tg3.h 477;" d -MAC_EXTADDR_3_HIGH tg3.h 478;" d -MAC_EXTADDR_3_LOW tg3.h 479;" d -MAC_EXTADDR_4_HIGH tg3.h 480;" d -MAC_EXTADDR_4_LOW tg3.h 481;" d -MAC_EXTADDR_5_HIGH tg3.h 482;" d -MAC_EXTADDR_5_LOW tg3.h 483;" d -MAC_EXTADDR_6_HIGH tg3.h 484;" d -MAC_EXTADDR_6_LOW tg3.h 485;" d -MAC_EXTADDR_7_HIGH tg3.h 486;" d -MAC_EXTADDR_7_LOW tg3.h 487;" d -MAC_EXTADDR_8_HIGH tg3.h 488;" d -MAC_EXTADDR_8_LOW tg3.h 489;" d -MAC_EXTADDR_9_HIGH tg3.h 490;" d -MAC_EXTADDR_9_LOW tg3.h 491;" d -MAC_HASHREGU_0 tg3.h 468;" d -MAC_HASHREGU_1 tg3.h 469;" d -MAC_HASHREGU_2 tg3.h 470;" d -MAC_HASHREGU_3 tg3.h 471;" d -MAC_HASH_REG_0 tg3.h 427;" d -MAC_HASH_REG_1 tg3.h 428;" d -MAC_HASH_REG_2 tg3.h 429;" d -MAC_HASH_REG_3 tg3.h 430;" d -MAC_LED_CTRL tg3.h 322;" d -MAC_LOW_WMARK_MAX_RX_FRAME tg3.h 466;" d -MAC_MI_COM tg3.h 369;" d -MAC_MI_MODE tg3.h 383;" d -MAC_MI_MODE_AUTO_POLL tg3.h 386;" d -MAC_MI_MODE_BASE tg3.h 388;" d -MAC_MI_MODE_CLK_10MHZ tg3.h 384;" d -MAC_MI_MODE_CORE_CLK_62MHZ tg3.h 387;" d -MAC_MI_MODE_SHORT_PREAMBLE tg3.h 385;" d -MAC_MI_STAT tg3.h 381;" d -MAC_MI_STAT_LNKSTAT_ATTN_ENAB tg3.h 382;" d -MAC_MODE tg3.h 273;" d -MAC_MODE_ACPI_ENABLE tg3.h 294;" d -MAC_MODE_FHDE_ENABLE tg3.h 298;" d -MAC_MODE_HALF_DUPLEX tg3.h 275;" d -MAC_MODE_LINK_POLARITY tg3.h 285;" d -MAC_MODE_MAGIC_PKT_ENABLE tg3.h 293;" d -MAC_MODE_MAX_DEFER tg3.h 284;" d -MAC_MODE_MIP_ENABLE tg3.h 295;" d -MAC_MODE_PORT_INT_LPBACK tg3.h 281;" d -MAC_MODE_PORT_MODE_GMII tg3.h 278;" d -MAC_MODE_PORT_MODE_MASK tg3.h 276;" d -MAC_MODE_PORT_MODE_MII tg3.h 279;" d -MAC_MODE_PORT_MODE_NONE tg3.h 280;" d -MAC_MODE_PORT_MODE_TBI tg3.h 277;" d -MAC_MODE_RDE_ENABLE tg3.h 297;" d -MAC_MODE_RESET tg3.h 274;" d -MAC_MODE_RXSTAT_CLEAR tg3.h 287;" d -MAC_MODE_RXSTAT_ENABLE tg3.h 286;" d -MAC_MODE_RXSTAT_FLUSH tg3.h 288;" d -MAC_MODE_SEND_CONFIGS tg3.h 292;" d -MAC_MODE_TAGGED_MAC_CTRL tg3.h 282;" d -MAC_MODE_TDE_ENABLE tg3.h 296;" d -MAC_MODE_TXSTAT_CLEAR tg3.h 290;" d -MAC_MODE_TXSTAT_ENABLE tg3.h 289;" d -MAC_MODE_TXSTAT_FLUSH tg3.h 291;" d -MAC_MODE_TX_BURSTING tg3.h 283;" d -MAC_PCS_TEST tg3.h 359;" d -MAC_RCV_RULE_0 tg3.h 431;" d -MAC_RCV_RULE_1 tg3.h 433;" d -MAC_RCV_RULE_10 tg3.h 451;" d -MAC_RCV_RULE_11 tg3.h 453;" d -MAC_RCV_RULE_12 tg3.h 455;" d -MAC_RCV_RULE_13 tg3.h 457;" d -MAC_RCV_RULE_14 tg3.h 459;" d -MAC_RCV_RULE_15 tg3.h 461;" d -MAC_RCV_RULE_2 tg3.h 435;" d -MAC_RCV_RULE_3 tg3.h 437;" d -MAC_RCV_RULE_4 tg3.h 439;" d -MAC_RCV_RULE_5 tg3.h 441;" d -MAC_RCV_RULE_6 tg3.h 443;" d -MAC_RCV_RULE_7 tg3.h 445;" d -MAC_RCV_RULE_8 tg3.h 447;" d -MAC_RCV_RULE_9 tg3.h 449;" d -MAC_RCV_RULE_CFG tg3.h 464;" d -MAC_RCV_VALUE_0 tg3.h 432;" d -MAC_RCV_VALUE_1 tg3.h 434;" d -MAC_RCV_VALUE_10 tg3.h 452;" d -MAC_RCV_VALUE_11 tg3.h 454;" d -MAC_RCV_VALUE_12 tg3.h 456;" d -MAC_RCV_VALUE_13 tg3.h 458;" d -MAC_RCV_VALUE_14 tg3.h 460;" d -MAC_RCV_VALUE_15 tg3.h 462;" d -MAC_RCV_VALUE_2 tg3.h 436;" d -MAC_RCV_VALUE_3 tg3.h 438;" d -MAC_RCV_VALUE_4 tg3.h 440;" d -MAC_RCV_VALUE_5 tg3.h 442;" d -MAC_RCV_VALUE_6 tg3.h 444;" d -MAC_RCV_VALUE_7 tg3.h 446;" d -MAC_RCV_VALUE_8 tg3.h 448;" d -MAC_RCV_VALUE_9 tg3.h 450;" d -MAC_RX_AUTO_NEG tg3.h 366;" d -MAC_RX_MAC_STATE_BASE tg3.h 500;" d -MAC_RX_MODE tg3.h 411;" d -MAC_RX_MTU_SIZE tg3.h 357;" d -MAC_RX_STATS_ALIGN_ERRORS tg3.h 541;" d -MAC_RX_STATS_BCAST tg3.h 539;" d -MAC_RX_STATS_FCS_ERRORS tg3.h 540;" d -MAC_RX_STATS_FRAGMENTS tg3.h 536;" d -MAC_RX_STATS_FRAME_TOO_LONG tg3.h 546;" d -MAC_RX_STATS_JABBERS tg3.h 547;" d -MAC_RX_STATS_MAC_CTRL_RECVD tg3.h 544;" d -MAC_RX_STATS_MCAST tg3.h 538;" d -MAC_RX_STATS_OCTETS tg3.h 534;" d -MAC_RX_STATS_RESV1 tg3.h 535;" d -MAC_RX_STATS_UCAST tg3.h 537;" d -MAC_RX_STATS_UNDERSIZE tg3.h 548;" d -MAC_RX_STATS_XOFF_ENTERED tg3.h 545;" d -MAC_RX_STATS_XOFF_PAUSE_RECVD tg3.h 543;" d -MAC_RX_STATS_XON_PAUSE_RECVD tg3.h 542;" d -MAC_RX_STATUS tg3.h 423;" d -MAC_SERDES_CFG tg3.h 496;" d -MAC_SERDES_STAT tg3.h 497;" d -MAC_STATUS tg3.h 299;" d -MAC_STATUS_AP_ERROR tg3.h 309;" d -MAC_STATUS_CFG_CHANGED tg3.h 303;" d -MAC_STATUS_LNKSTATE_CHANGED tg3.h 306;" d -MAC_STATUS_MI_COMPLETION tg3.h 307;" d -MAC_STATUS_MI_INTERRUPT tg3.h 308;" d -MAC_STATUS_ODI_ERROR tg3.h 310;" d -MAC_STATUS_PCS_SYNCED tg3.h 300;" d -MAC_STATUS_PORT_DEC_ERR tg3.h 305;" d -MAC_STATUS_RCVD_CFG tg3.h 302;" d -MAC_STATUS_RXSTAT_OVERRUN tg3.h 311;" d -MAC_STATUS_SIGNAL_DET tg3.h 301;" d -MAC_STATUS_SYNC_CHANGED tg3.h 304;" d -MAC_STATUS_TXSTAT_OVERRUN tg3.h 312;" d -MAC_TX_AUTO_NEG tg3.h 363;" d -MAC_TX_BACKOFF_SEED tg3.h 355;" d -MAC_TX_LENGTHS tg3.h 404;" d -MAC_TX_MAC_STATE_BASE tg3.h 499;" d -MAC_TX_MODE tg3.h 391;" d -MAC_TX_STATS_BCAST tg3.h 531;" d -MAC_TX_STATS_COLLISIONS tg3.h 504;" d -MAC_TX_STATS_DEFERRED tg3.h 511;" d -MAC_TX_STATS_EXCESSIVE_COL tg3.h 513;" d -MAC_TX_STATS_LATE_COL tg3.h 514;" d -MAC_TX_STATS_MAC_ERRORS tg3.h 508;" d -MAC_TX_STATS_MCAST tg3.h 530;" d -MAC_TX_STATS_MULT_COLLISIONS tg3.h 510;" d -MAC_TX_STATS_OCTETS tg3.h 502;" d -MAC_TX_STATS_RESV1 tg3.h 503;" d -MAC_TX_STATS_RESV2 tg3.h 507;" d -MAC_TX_STATS_RESV3 tg3.h 512;" d -MAC_TX_STATS_RESV4_1 tg3.h 515;" d -MAC_TX_STATS_RESV4_10 tg3.h 524;" d -MAC_TX_STATS_RESV4_11 tg3.h 525;" d -MAC_TX_STATS_RESV4_12 tg3.h 526;" d -MAC_TX_STATS_RESV4_13 tg3.h 527;" d -MAC_TX_STATS_RESV4_14 tg3.h 528;" d -MAC_TX_STATS_RESV4_2 tg3.h 516;" d -MAC_TX_STATS_RESV4_3 tg3.h 517;" d -MAC_TX_STATS_RESV4_4 tg3.h 518;" d -MAC_TX_STATS_RESV4_5 tg3.h 519;" d -MAC_TX_STATS_RESV4_6 tg3.h 520;" d -MAC_TX_STATS_RESV4_7 tg3.h 521;" d -MAC_TX_STATS_RESV4_8 tg3.h 522;" d -MAC_TX_STATS_RESV4_9 tg3.h 523;" d -MAC_TX_STATS_RESV5_1 tg3.h 532;" d -MAC_TX_STATS_RESV5_2 tg3.h 533;" d -MAC_TX_STATS_SINGLE_COLLISIONS tg3.h 509;" d -MAC_TX_STATS_UCAST tg3.h 529;" d -MAC_TX_STATS_XOFF_SENT tg3.h 506;" d -MAC_TX_STATS_XON_SENT tg3.h 505;" d -MAC_TX_STATUS tg3.h 397;" d -MAILBOX_GENERAL_0 tg3.h 211;" d -MAILBOX_GENERAL_1 tg3.h 212;" d -MAILBOX_GENERAL_2 tg3.h 213;" d -MAILBOX_GENERAL_3 tg3.h 214;" d -MAILBOX_GENERAL_4 tg3.h 215;" d -MAILBOX_GENERAL_5 tg3.h 216;" d -MAILBOX_GENERAL_6 tg3.h 217;" d -MAILBOX_GENERAL_7 tg3.h 218;" d -MAILBOX_INTERRUPT_0 tg3.h 207;" d -MAILBOX_INTERRUPT_1 tg3.h 208;" d -MAILBOX_INTERRUPT_2 tg3.h 209;" d -MAILBOX_INTERRUPT_3 tg3.h 210;" d -MAILBOX_RCVRET_CON_IDX_0 tg3.h 223;" d -MAILBOX_RCVRET_CON_IDX_1 tg3.h 224;" d -MAILBOX_RCVRET_CON_IDX_10 tg3.h 233;" d -MAILBOX_RCVRET_CON_IDX_11 tg3.h 234;" d -MAILBOX_RCVRET_CON_IDX_12 tg3.h 235;" d -MAILBOX_RCVRET_CON_IDX_13 tg3.h 236;" d -MAILBOX_RCVRET_CON_IDX_14 tg3.h 237;" d -MAILBOX_RCVRET_CON_IDX_15 tg3.h 238;" d -MAILBOX_RCVRET_CON_IDX_2 tg3.h 225;" d -MAILBOX_RCVRET_CON_IDX_3 tg3.h 226;" d -MAILBOX_RCVRET_CON_IDX_4 tg3.h 227;" d -MAILBOX_RCVRET_CON_IDX_5 tg3.h 228;" d -MAILBOX_RCVRET_CON_IDX_6 tg3.h 229;" d -MAILBOX_RCVRET_CON_IDX_7 tg3.h 230;" d -MAILBOX_RCVRET_CON_IDX_8 tg3.h 231;" d -MAILBOX_RCVRET_CON_IDX_9 tg3.h 232;" d -MAILBOX_RCV_JUMBO_PROD_IDX tg3.h 221;" d -MAILBOX_RCV_MINI_PROD_IDX tg3.h 222;" d -MAILBOX_RCV_STD_PROD_IDX tg3.h 220;" d -MAILBOX_RELOAD_STAT tg3.h 219;" d -MAILBOX_SNDHOST_PROD_IDX_0 tg3.h 239;" d -MAILBOX_SNDHOST_PROD_IDX_1 tg3.h 240;" d -MAILBOX_SNDHOST_PROD_IDX_10 tg3.h 249;" d -MAILBOX_SNDHOST_PROD_IDX_11 tg3.h 250;" d -MAILBOX_SNDHOST_PROD_IDX_12 tg3.h 251;" d -MAILBOX_SNDHOST_PROD_IDX_13 tg3.h 252;" d -MAILBOX_SNDHOST_PROD_IDX_14 tg3.h 253;" d -MAILBOX_SNDHOST_PROD_IDX_15 tg3.h 254;" d -MAILBOX_SNDHOST_PROD_IDX_2 tg3.h 241;" d -MAILBOX_SNDHOST_PROD_IDX_3 tg3.h 242;" d -MAILBOX_SNDHOST_PROD_IDX_4 tg3.h 243;" d -MAILBOX_SNDHOST_PROD_IDX_5 tg3.h 244;" d -MAILBOX_SNDHOST_PROD_IDX_6 tg3.h 245;" d -MAILBOX_SNDHOST_PROD_IDX_7 tg3.h 246;" d -MAILBOX_SNDHOST_PROD_IDX_8 tg3.h 247;" d -MAILBOX_SNDHOST_PROD_IDX_9 tg3.h 248;" d -MAILBOX_SNDNIC_PROD_IDX_0 tg3.h 255;" d -MAILBOX_SNDNIC_PROD_IDX_1 tg3.h 256;" d -MAILBOX_SNDNIC_PROD_IDX_10 tg3.h 265;" d -MAILBOX_SNDNIC_PROD_IDX_11 tg3.h 266;" d -MAILBOX_SNDNIC_PROD_IDX_12 tg3.h 267;" d -MAILBOX_SNDNIC_PROD_IDX_13 tg3.h 268;" d -MAILBOX_SNDNIC_PROD_IDX_14 tg3.h 269;" d -MAILBOX_SNDNIC_PROD_IDX_15 tg3.h 270;" d -MAILBOX_SNDNIC_PROD_IDX_2 tg3.h 257;" d -MAILBOX_SNDNIC_PROD_IDX_3 tg3.h 258;" d -MAILBOX_SNDNIC_PROD_IDX_4 tg3.h 259;" d -MAILBOX_SNDNIC_PROD_IDX_5 tg3.h 260;" d -MAILBOX_SNDNIC_PROD_IDX_6 tg3.h 261;" d -MAILBOX_SNDNIC_PROD_IDX_7 tg3.h 262;" d -MAILBOX_SNDNIC_PROD_IDX_8 tg3.h 263;" d -MAILBOX_SNDNIC_PROD_IDX_9 tg3.h 264;" d -MAX_WAIT_CNT tg3.c 3296;" d file: -MBFREE_MODE tg3.h 781;" d -MBFREE_MODE_ENABLE tg3.h 783;" d -MBFREE_MODE_RESET tg3.h 782;" d -MBFREE_STATUS tg3.h 784;" d -MEMARB_MODE tg3.h 874;" d -MEMARB_MODE_ENABLE tg3.h 876;" d -MEMARB_MODE_RESET tg3.h 875;" d -MEMARB_STATUS tg3.h 877;" d -MEMARB_TRAP_ADDR_HIGH tg3.h 879;" d -MEMARB_TRAP_ADDR_LOW tg3.h 878;" d -METAL_REV_A0 tg3.h 133;" d -METAL_REV_A1 tg3.h 134;" d -METAL_REV_B0 tg3.h 135;" d -METAL_REV_B1 tg3.h 136;" d -METAL_REV_B2 tg3.h 137;" d -MII_TG3_AUX_CTRL tg3.h 1431;" d -MII_TG3_AUX_STAT tg3.h 1433;" d -MII_TG3_AUX_STAT_1000FULL tg3.h 1442;" d -MII_TG3_AUX_STAT_1000HALF tg3.h 1441;" d -MII_TG3_AUX_STAT_100FULL tg3.h 1440;" d -MII_TG3_AUX_STAT_100HALF tg3.h 1438;" d -MII_TG3_AUX_STAT_100_4 tg3.h 1439;" d -MII_TG3_AUX_STAT_10FULL tg3.h 1437;" d -MII_TG3_AUX_STAT_10HALF tg3.h 1436;" d -MII_TG3_AUX_STAT_LPASS tg3.h 1434;" d -MII_TG3_AUX_STAT_SPDMASK tg3.h 1435;" d -MII_TG3_CTRL tg3.h 1414;" d -MII_TG3_CTRL_ADV_1000_FULL tg3.h 1416;" d -MII_TG3_CTRL_ADV_1000_HALF tg3.h 1415;" d -MII_TG3_CTRL_AS_MASTER tg3.h 1417;" d -MII_TG3_CTRL_ENABLE_AS_MASTER tg3.h 1418;" d -MII_TG3_DSP_ADDRESS tg3.h 1429;" d -MII_TG3_DSP_RW_PORT tg3.h 1427;" d -MII_TG3_EXT_CTRL tg3.h 1420;" d -MII_TG3_EXT_CTRL_LNK3_LED_MODE tg3.h 1421;" d -MII_TG3_EXT_CTRL_TBI tg3.h 1422;" d -MII_TG3_EXT_STAT tg3.h 1424;" d -MII_TG3_EXT_STAT_LPASS tg3.h 1425;" d -MII_TG3_IMASK tg3.h 1445;" d -MII_TG3_INT_ANEG_PAGE_RX tg3.h 1451;" d -MII_TG3_INT_DUPLEXCHG tg3.h 1450;" d -MII_TG3_INT_LINKCHG tg3.h 1448;" d -MII_TG3_INT_SPEEDCHG tg3.h 1449;" d -MII_TG3_ISTAT tg3.h 1444;" d -MISC_HOST_CTRL_BYTE_SWAP tg3.h 88;" d -MISC_HOST_CTRL_CHIPREV tg3.h 96;" d -MISC_HOST_CTRL_CHIPREV_SHIFT tg3.h 97;" d -MISC_HOST_CTRL_CLEAR_INT tg3.h 86;" d -MISC_HOST_CTRL_CLKREG_RW tg3.h 91;" d -MISC_HOST_CTRL_INDIR_ACCESS tg3.h 93;" d -MISC_HOST_CTRL_IRQ_MASK_MODE tg3.h 94;" d -MISC_HOST_CTRL_MASK_PCI_INT tg3.h 87;" d -MISC_HOST_CTRL_PCISTATE_RW tg3.h 90;" d -MISC_HOST_CTRL_REGWORD_SWAP tg3.h 92;" d -MISC_HOST_CTRL_TAGGED_STATUS tg3.h 95;" d -MISC_HOST_CTRL_WORD_SWAP tg3.h 89;" d -MI_COM_BUSY tg3.h 375;" d -MI_COM_CMD_MASK tg3.h 370;" d -MI_COM_CMD_READ tg3.h 372;" d -MI_COM_CMD_WRITE tg3.h 371;" d -MI_COM_DATA_MASK tg3.h 380;" d -MI_COM_PHY_ADDR_MASK tg3.h 376;" d -MI_COM_PHY_ADDR_SHIFT tg3.h 377;" d -MI_COM_READ_FAILED tg3.h 373;" d -MI_COM_REG_ADDR_MASK tg3.h 378;" d -MI_COM_REG_ADDR_SHIFT tg3.h 379;" d -MI_COM_START tg3.h 374;" d -MR_AN_COMPLETE tg3.c 1479;" d file: -MR_AN_ENABLE tg3.c 1477;" d file: -MR_LINK_OK tg3.c 1493;" d file: -MR_LP_ADV_ASYM_PAUSE tg3.c 1486;" d file: -MR_LP_ADV_FULL_DUPLEX tg3.c 1483;" d file: -MR_LP_ADV_HALF_DUPLEX tg3.c 1484;" d file: -MR_LP_ADV_NEXT_PAGE tg3.c 1489;" d file: -MR_LP_ADV_REMOTE_FAULT1 tg3.c 1487;" d file: -MR_LP_ADV_REMOTE_FAULT2 tg3.c 1488;" d file: -MR_LP_ADV_SYM_PAUSE tg3.c 1485;" d file: -MR_NP_LOADED tg3.c 1481;" d file: -MR_NP_RX tg3.c 1491;" d file: -MR_PAGE_RX tg3.c 1480;" d file: -MR_RESTART_AN tg3.c 1478;" d file: -MR_TOGGLE_RX tg3.c 1490;" d file: -MR_TOGGLE_TX tg3.c 1482;" d file: -MSGINT_FIFO tg3.h 1182;" d -MSGINT_MODE tg3.h 1178;" d -MSGINT_MODE_ENABLE tg3.h 1180;" d -MSGINT_MODE_RESET tg3.h 1179;" d -MSGINT_STATUS tg3.h 1181;" d -NEXT_TX tg3.c 121;" d file: -NIC_SRAM_DATA_CFG tg3.h 1353;" d -NIC_SRAM_DATA_CFG_ASF_ENABLE tg3.h 1365;" d -NIC_SRAM_DATA_CFG_EEPROM_WP tg3.h 1366;" d -NIC_SRAM_DATA_CFG_FIBER_WOL tg3.h 1368;" d -NIC_SRAM_DATA_CFG_LED_LINK_SPD tg3.h 1358;" d -NIC_SRAM_DATA_CFG_LED_MODE_MASK tg3.h 1354;" d -NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN tg3.h 1355;" d -NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN tg3.h 1357;" d -NIC_SRAM_DATA_CFG_LED_OUTPUT tg3.h 1359;" d -NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD tg3.h 1356;" d -NIC_SRAM_DATA_CFG_MINI_PCI tg3.h 1367;" d -NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER tg3.h 1362;" d -NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER tg3.h 1363;" d -NIC_SRAM_DATA_CFG_PHY_TYPE_MASK tg3.h 1360;" d -NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN tg3.h 1361;" d -NIC_SRAM_DATA_CFG_WOL_ENABLE tg3.h 1364;" d -NIC_SRAM_DATA_PHY_ID tg3.h 1370;" d -NIC_SRAM_DATA_PHY_ID1_MASK tg3.h 1371;" d -NIC_SRAM_DATA_PHY_ID2_MASK tg3.h 1372;" d -NIC_SRAM_DATA_SIG tg3.h 1350;" d -NIC_SRAM_DATA_SIG_MAGIC tg3.h 1351;" d -NIC_SRAM_DMA_DESC_POOL_BASE tg3.h 1397;" d -NIC_SRAM_DMA_DESC_POOL_SIZE tg3.h 1398;" d -NIC_SRAM_FIRMWARE_MBOX tg3.h 1346;" d -NIC_SRAM_FIRMWARE_MBOX_MAGIC1 tg3.h 1347;" d -NIC_SRAM_FIRMWARE_MBOX_MAGIC2 tg3.h 1348;" d -NIC_SRAM_FW_ASF_STATUS_MBOX tg3.h 1383;" d -NIC_SRAM_FW_CMD_DATA_MBOX tg3.h 1382;" d -NIC_SRAM_FW_CMD_LEN_MBOX tg3.h 1381;" d -NIC_SRAM_FW_CMD_MBOX tg3.h 1374;" d -NIC_SRAM_FW_DRV_STATE_MBOX tg3.h 1384;" d -NIC_SRAM_FW_RESET_TYPE_MBOX tg3.h 1390;" d -NIC_SRAM_MAC_ADDR_HIGH_MBOX tg3.h 1392;" d -NIC_SRAM_MAC_ADDR_LOW_MBOX tg3.h 1393;" d -NIC_SRAM_MBUF_POOL_BASE tg3.h 1402;" d -NIC_SRAM_MBUF_POOL_BASE5705 tg3.h 1405;" d -NIC_SRAM_MBUF_POOL_SIZE5705 tg3.h 1406;" d -NIC_SRAM_MBUF_POOL_SIZE64 tg3.h 1404;" d -NIC_SRAM_MBUF_POOL_SIZE96 tg3.h 1403;" d -NIC_SRAM_PAGE_ZERO tg3.h 1340;" d -NIC_SRAM_RCV_RET_RCB tg3.h 1342;" d -NIC_SRAM_RX_BUFFER_DESC tg3.h 1400;" d -NIC_SRAM_RX_JUMBO_BUFFER_DESC tg3.h 1401;" d -NIC_SRAM_RX_MINI_BUFFER_DESC tg3.h 1395;" d -NIC_SRAM_SEND_RCB tg3.h 1341;" d -NIC_SRAM_STATS_BLK tg3.h 1343;" d -NIC_SRAM_STATUS_BLK tg3.h 1344;" d -NIC_SRAM_TX_BUFFER_DESC tg3.h 1399;" d -NIC_SRAM_WIN_BASE tg3.h 1337;" d -NVRAM_ADDR tg3.h 1302;" d -NVRAM_ADDR_MSK tg3.h 1303;" d -NVRAM_BUFFERED_PAGE_POS tg3.h 1331;" d -NVRAM_BUFFERED_PAGE_SIZE tg3.h 1330;" d -NVRAM_CFG1 tg3.h 1305;" d -NVRAM_CFG1_BIT_BANG tg3.h 1309;" d -NVRAM_CFG1_BUFFERED_MODE tg3.h 1307;" d -NVRAM_CFG1_COMPAT_BYPASS tg3.h 1310;" d -NVRAM_CFG1_FLASHIF_ENAB tg3.h 1306;" d -NVRAM_CFG1_PASS_THRU tg3.h 1308;" d -NVRAM_CFG2 tg3.h 1311;" d -NVRAM_CFG3 tg3.h 1312;" d -NVRAM_CMD tg3.h 1291;" d -NVRAM_CMD_DONE tg3.h 1293;" d -NVRAM_CMD_ERASE tg3.h 1297;" d -NVRAM_CMD_FIRST tg3.h 1298;" d -NVRAM_CMD_GO tg3.h 1294;" d -NVRAM_CMD_LAST tg3.h 1299;" d -NVRAM_CMD_RD tg3.h 1296;" d -NVRAM_CMD_RESET tg3.h 1292;" d -NVRAM_CMD_WR tg3.h 1295;" d -NVRAM_RDDATA tg3.h 1304;" d -NVRAM_STAT tg3.h 1300;" d -NVRAM_SWARB tg3.h 1313;" d -NVRAM_WRDATA tg3.h 1301;" d -PCISTATE_BUS_32BIT tg3.h 175;" d -PCISTATE_BUS_SPEED_HIGH tg3.h 174;" d -PCISTATE_CONV_PCI_MODE tg3.h 173;" d -PCISTATE_FLAT_VIEW tg3.h 178;" d -PCISTATE_FORCE_RESET tg3.h 171;" d -PCISTATE_INT_NOT_ACTIVE tg3.h 172;" d -PCISTATE_RETRY_SAME_DMA tg3.h 179;" d -PCISTATE_ROM_ENABLE tg3.h 176;" d -PCISTATE_ROM_RETRY_ENABLE tg3.h 177;" d -PCIX_CAPS_BURST_MASK tg3.h 61;" d -PCIX_CAPS_BURST_SHIFT tg3.h 62;" d -PCIX_CAPS_MAX_BURST_CPIOB tg3.h 63;" d -PCIX_CAPS_RELAXED_ORDERING tg3.h 58;" d -PCIX_CAPS_SPLIT_MASK tg3.h 59;" d -PCIX_CAPS_SPLIT_SHIFT tg3.h 60;" d -PCS_TEST_ENABLE tg3.h 362;" d -PCS_TEST_PATTERN_MASK tg3.h 360;" d -PCS_TEST_PATTERN_SHIFT tg3.h 361;" d -PFX tg3.c 58;" d file: -PHY_ADDR tg3.h 1409;" d -PHY_BUSY_LOOPS tg3.c 315;" d file: -PHY_ID_BCM5400 tg3.h 1961;" d -PHY_ID_BCM5401 tg3.h 1962;" d -PHY_ID_BCM5411 tg3.h 1963;" d -PHY_ID_BCM5701 tg3.h 1964;" d -PHY_ID_BCM5703 tg3.h 1965;" d -PHY_ID_BCM5704 tg3.h 1966;" d -PHY_ID_BCM5705 tg3.h 1967;" d -PHY_ID_BCM8002 tg3.h 1968;" d -PHY_ID_INVALID tg3.h 1970;" d -PHY_ID_MASK tg3.h 1960;" d -PHY_ID_REV_MASK tg3.h 1971;" d -PHY_ID_SERDES tg3.h 1969;" d -PHY_REV_BCM5401_B0 tg3.h 1972;" d -PHY_REV_BCM5401_B2 tg3.h 1973;" d -PHY_REV_BCM5401_C0 tg3.h 1974;" d -PHY_REV_BCM5411_X0 tg3.h 1975;" d -RCVBDI_JUMBO_PROD_IDX tg3.h 751;" d -RCVBDI_JUMBO_THRESH tg3.h 756;" d -RCVBDI_MINI_PROD_IDX tg3.h 753;" d -RCVBDI_MINI_THRESH tg3.h 754;" d -RCVBDI_MODE tg3.h 745;" d -RCVBDI_MODE_ENABLE tg3.h 747;" d -RCVBDI_MODE_RCB_ATTN_ENAB tg3.h 748;" d -RCVBDI_MODE_RESET tg3.h 746;" d -RCVBDI_STATUS tg3.h 749;" d -RCVBDI_STATUS_RCB_ATTN tg3.h 750;" d -RCVBDI_STD_PROD_IDX tg3.h 752;" d -RCVBDI_STD_THRESH tg3.h 755;" d -RCVCC_JUMP_PROD_IDX tg3.h 766;" d -RCVCC_MINI_PROD_IDX tg3.h 768;" d -RCVCC_MODE tg3.h 760;" d -RCVCC_MODE_ATTN_ENABLE tg3.h 763;" d -RCVCC_MODE_ENABLE tg3.h 762;" d -RCVCC_MODE_RESET tg3.h 761;" d -RCVCC_STATUS tg3.h 764;" d -RCVCC_STATUS_ERROR_ATTN tg3.h 765;" d -RCVCC_STD_PROD_IDX tg3.h 767;" d -RCVDBDI_BD_PROD_IDX_0 tg3.h 718;" d -RCVDBDI_BD_PROD_IDX_1 tg3.h 719;" d -RCVDBDI_BD_PROD_IDX_10 tg3.h 728;" d -RCVDBDI_BD_PROD_IDX_11 tg3.h 729;" d -RCVDBDI_BD_PROD_IDX_12 tg3.h 730;" d -RCVDBDI_BD_PROD_IDX_13 tg3.h 731;" d -RCVDBDI_BD_PROD_IDX_14 tg3.h 732;" d -RCVDBDI_BD_PROD_IDX_15 tg3.h 733;" d -RCVDBDI_BD_PROD_IDX_2 tg3.h 720;" d -RCVDBDI_BD_PROD_IDX_3 tg3.h 721;" d -RCVDBDI_BD_PROD_IDX_4 tg3.h 722;" d -RCVDBDI_BD_PROD_IDX_5 tg3.h 723;" d -RCVDBDI_BD_PROD_IDX_6 tg3.h 724;" d -RCVDBDI_BD_PROD_IDX_7 tg3.h 725;" d -RCVDBDI_BD_PROD_IDX_8 tg3.h 726;" d -RCVDBDI_BD_PROD_IDX_9 tg3.h 727;" d -RCVDBDI_HWDIAG tg3.h 734;" d -RCVDBDI_JUMBO_BD tg3.h 711;" d -RCVDBDI_JUMBO_CON_IDX tg3.h 714;" d -RCVDBDI_MINI_BD tg3.h 713;" d -RCVDBDI_MINI_CON_IDX tg3.h 716;" d -RCVDBDI_MODE tg3.h 699;" d -RCVDBDI_MODE_ENABLE tg3.h 701;" d -RCVDBDI_MODE_FRM_TOO_BIG tg3.h 703;" d -RCVDBDI_MODE_INV_RING_SZ tg3.h 704;" d -RCVDBDI_MODE_JUMBOBD_NEEDED tg3.h 702;" d -RCVDBDI_MODE_RESET tg3.h 700;" d -RCVDBDI_SPLIT_FRAME_MINSZ tg3.h 709;" d -RCVDBDI_STATUS tg3.h 705;" d -RCVDBDI_STATUS_FRM_TOO_BIG tg3.h 707;" d -RCVDBDI_STATUS_INV_RING_SZ tg3.h 708;" d -RCVDBDI_STATUS_JUMBOBD_NEEDED tg3.h 706;" d -RCVDBDI_STD_BD tg3.h 712;" d -RCVDBDI_STD_CON_IDX tg3.h 715;" d -RCVDCC_MODE tg3.h 738;" d -RCVDCC_MODE_ATTN_ENABLE tg3.h 741;" d -RCVDCC_MODE_ENABLE tg3.h 740;" d -RCVDCC_MODE_RESET tg3.h 739;" d -RCVLPC_CONFIG tg3.h 676;" d -RCVLPC_COS_CNTL_BASE tg3.h 688;" d -RCVLPC_DMA_HIPRIO_WQ_FULL_CNT tg3.h 691;" d -RCVLPC_DMA_WQ_FULL_CNT tg3.h 690;" d -RCVLPC_DROP_FILTER_CNT tg3.h 689;" d -RCVLPC_IN_DISCARDS_CNT tg3.h 693;" d -RCVLPC_IN_ERRORS_CNT tg3.h 694;" d -RCVLPC_LOCK tg3.h 669;" d -RCVLPC_LOCK_GRANT_MASK tg3.h 672;" d -RCVLPC_LOCK_GRANT_SHIFT tg3.h 673;" d -RCVLPC_LOCK_REQ_MASK tg3.h 670;" d -RCVLPC_LOCK_REQ_SHIFT tg3.h 671;" d -RCVLPC_MODE tg3.h 659;" d -RCVLPC_MODE_CLASS0_ATTN_ENAB tg3.h 662;" d -RCVLPC_MODE_ENABLE tg3.h 661;" d -RCVLPC_MODE_MAPOOR_AATTN_ENAB tg3.h 663;" d -RCVLPC_MODE_RESET tg3.h 660;" d -RCVLPC_MODE_STAT_OFLOW_ENAB tg3.h 664;" d -RCVLPC_NON_EMPTY_BITS tg3.h 674;" d -RCVLPC_NON_EMPTY_BITS_MASK tg3.h 675;" d -RCVLPC_NO_RCV_BD_CNT tg3.h 692;" d -RCVLPC_RCV_THRESH_HIT_CNT tg3.h 695;" d -RCVLPC_SELLST_BASE tg3.h 684;" d -RCVLPC_STATSCTRL tg3.h 677;" d -RCVLPC_STATSCTRL_ENABLE tg3.h 678;" d -RCVLPC_STATSCTRL_FASTUPD tg3.h 679;" d -RCVLPC_STATSENAB_LNGBRST_RFIX tg3.h 681;" d -RCVLPC_STATS_ENABLE tg3.h 680;" d -RCVLPC_STATS_INCMASK tg3.h 682;" d -RCVLPC_STATUS tg3.h 665;" d -RCVLPC_STATUS_CLASS0 tg3.h 666;" d -RCVLPC_STATUS_MAPOOR tg3.h 667;" d -RCVLPC_STATUS_STAT_OFLOW tg3.h 668;" d -RCVLSC_MODE tg3.h 772;" d -RCVLSC_MODE_ATTN_ENABLE tg3.h 775;" d -RCVLSC_MODE_ENABLE tg3.h 774;" d -RCVLSC_MODE_RESET tg3.h 773;" d -RCVLSC_STATUS tg3.h 776;" d -RCVLSC_STATUS_ERROR_ATTN tg3.h 777;" d -RCV_RULE_CFG_DEFAULT_CLASS tg3.h 465;" d -RCV_RULE_DISABLE_MASK tg3.h 463;" d -RDMAC_MODE tg3.h 927;" d -RDMAC_MODE_ADDROFLOW_ENAB tg3.h 933;" d -RDMAC_MODE_ENABLE tg3.h 929;" d -RDMAC_MODE_FIFOOFLOW_ENAB tg3.h 934;" d -RDMAC_MODE_FIFOOREAD_ENAB tg3.h 936;" d -RDMAC_MODE_FIFOURUN_ENAB tg3.h 935;" d -RDMAC_MODE_FIFO_LONG_BURST tg3.h 941;" d -RDMAC_MODE_FIFO_SIZE_128 tg3.h 940;" d -RDMAC_MODE_LNGREAD_ENAB tg3.h 937;" d -RDMAC_MODE_MSTABORT_ENAB tg3.h 931;" d -RDMAC_MODE_PARITYERR_ENAB tg3.h 932;" d -RDMAC_MODE_RESET tg3.h 928;" d -RDMAC_MODE_SPLIT_ENABLE tg3.h 938;" d -RDMAC_MODE_SPLIT_RESET tg3.h 939;" d -RDMAC_MODE_TGTABORT_ENAB tg3.h 930;" d -RDMAC_STATUS tg3.h 942;" d -RDMAC_STATUS_ADDROFLOW tg3.h 946;" d -RDMAC_STATUS_FIFOOFLOW tg3.h 947;" d -RDMAC_STATUS_FIFOOREAD tg3.h 949;" d -RDMAC_STATUS_FIFOURUN tg3.h 948;" d -RDMAC_STATUS_LNGREAD tg3.h 950;" d -RDMAC_STATUS_MSTABORT tg3.h 944;" d -RDMAC_STATUS_PARITYERR tg3.h 945;" d -RDMAC_STATUS_TGTABORT tg3.h 943;" d -RXD_ERR_BAD_CRC tg3.h 1565;" d -RXD_ERR_COLLISION tg3.h 1566;" d -RXD_ERR_HUGE_FRAME tg3.h 1573;" d -RXD_ERR_LINK_LOST tg3.h 1567;" d -RXD_ERR_MAC_ABRT tg3.h 1570;" d -RXD_ERR_MASK tg3.h 1574;" d -RXD_ERR_NO_RESOURCES tg3.h 1572;" d -RXD_ERR_ODD_NIBBLE_RCVD_MII tg3.h 1569;" d -RXD_ERR_PHY_DECODE tg3.h 1568;" d -RXD_ERR_TOO_SMALL tg3.h 1571;" d -RXD_FLAGS_SHIFT tg3.h 1544;" d -RXD_FLAG_END tg3.h 1546;" d -RXD_FLAG_ERROR tg3.h 1550;" d -RXD_FLAG_IP_CSUM tg3.h 1551;" d -RXD_FLAG_IS_TCP tg3.h 1553;" d -RXD_FLAG_JUMBO tg3.h 1548;" d -RXD_FLAG_MINI tg3.h 1547;" d -RXD_FLAG_TCPUDP_CSUM tg3.h 1552;" d -RXD_FLAG_VLAN tg3.h 1549;" d -RXD_IDX_MASK tg3.h 1537;" d -RXD_IDX_SHIFT tg3.h 1538;" d -RXD_IPCSUM_MASK tg3.h 1556;" d -RXD_IPCSUM_SHIFT tg3.h 1557;" d -RXD_LEN_MASK tg3.h 1539;" d -RXD_LEN_SHIFT tg3.h 1540;" d -RXD_OPAQUE_INDEX_MASK tg3.h 1578;" d -RXD_OPAQUE_INDEX_SHIFT tg3.h 1579;" d -RXD_OPAQUE_RING_JUMBO tg3.h 1581;" d -RXD_OPAQUE_RING_MASK tg3.h 1583;" d -RXD_OPAQUE_RING_MINI tg3.h 1582;" d -RXD_OPAQUE_RING_STD tg3.h 1580;" d -RXD_TCPCSUM_MASK tg3.h 1558;" d -RXD_TCPCSUM_SHIFT tg3.h 1559;" d -RXD_TYPE_SHIFT tg3.h 1543;" d -RXD_VLAN_MASK tg3.h 1563;" d -RX_AUTO_NEG_MASK tg3.h 367;" d -RX_AUTO_NEG_SHIFT tg3.h 368;" d -RX_COPY_THRESHOLD tg3.h 24;" d -RX_CPU_BASE tg3.h 1030;" d -RX_CPU_SCRATCH_BASE tg3.c 3681;" d file: -RX_CPU_SCRATCH_SIZE tg3.c 3682;" d file: -RX_JUMBO_MAX_SIZE tg3.h 28;" d -RX_JUMBO_PKT_BUF_SZ tg3.c 124;" d file: -RX_MODE_ACCEPT_OVERSIZED tg3.h 417;" d -RX_MODE_ACCEPT_RUNTS tg3.h 418;" d -RX_MODE_ENABLE tg3.h 413;" d -RX_MODE_FLOW_CTRL_ENABLE tg3.h 414;" d -RX_MODE_KEEP_MAC_CTRL tg3.h 415;" d -RX_MODE_KEEP_PAUSE tg3.h 416;" d -RX_MODE_KEEP_VLAN_TAG tg3.h 422;" d -RX_MODE_LEN_CHECK tg3.h 419;" d -RX_MODE_NO_CRC_CHECK tg3.h 421;" d -RX_MODE_PROMISC tg3.h 420;" d -RX_MODE_RESET tg3.h 412;" d -RX_MTU_SIZE_MASK tg3.h 358;" d -RX_PKT_BUF_SZ tg3.c 123;" d file: -RX_STATUS_REMOTE_TX_XOFFED tg3.h 424;" d -RX_STATUS_XOFF_RCVD tg3.h 425;" d -RX_STATUS_XON_RCVD tg3.h 426;" d -RX_STD_MAX_SIZE tg3.h 26;" d -RX_STD_MAX_SIZE_5705 tg3.h 27;" d -SD_STATUS_ERROR tg3.h 1623;" d -SD_STATUS_LINK_CHG tg3.h 1622;" d -SD_STATUS_UPDATED tg3.h 1621;" d -SELLST_CONT tg3.h 686;" d -SELLST_TAIL tg3.h 685;" d -SELLST_UNUSED tg3.h 687;" d -SNDBDC_MODE tg3.h 652;" d -SNDBDC_MODE_ATTN_ENABLE tg3.h 655;" d -SNDBDC_MODE_ENABLE tg3.h 654;" d -SNDBDC_MODE_RESET tg3.h 653;" d -SNDBDI_IN_PROD_IDX_0 tg3.h 633;" d -SNDBDI_IN_PROD_IDX_1 tg3.h 634;" d -SNDBDI_IN_PROD_IDX_10 tg3.h 643;" d -SNDBDI_IN_PROD_IDX_11 tg3.h 644;" d -SNDBDI_IN_PROD_IDX_12 tg3.h 645;" d -SNDBDI_IN_PROD_IDX_13 tg3.h 646;" d -SNDBDI_IN_PROD_IDX_14 tg3.h 647;" d -SNDBDI_IN_PROD_IDX_15 tg3.h 648;" d -SNDBDI_IN_PROD_IDX_2 tg3.h 635;" d -SNDBDI_IN_PROD_IDX_3 tg3.h 636;" d -SNDBDI_IN_PROD_IDX_4 tg3.h 637;" d -SNDBDI_IN_PROD_IDX_5 tg3.h 638;" d -SNDBDI_IN_PROD_IDX_6 tg3.h 639;" d -SNDBDI_IN_PROD_IDX_7 tg3.h 640;" d -SNDBDI_IN_PROD_IDX_8 tg3.h 641;" d -SNDBDI_IN_PROD_IDX_9 tg3.h 642;" d -SNDBDI_MODE tg3.h 627;" d -SNDBDI_MODE_ATTN_ENABLE tg3.h 630;" d -SNDBDI_MODE_ENABLE tg3.h 629;" d -SNDBDI_MODE_RESET tg3.h 628;" d -SNDBDI_STATUS tg3.h 631;" d -SNDBDI_STATUS_ERROR_ATTN tg3.h 632;" d -SNDBDS_HWDIAG tg3.h 606;" d -SNDBDS_MODE tg3.h 600;" d -SNDBDS_MODE_ATTN_ENABLE tg3.h 603;" d -SNDBDS_MODE_ENABLE tg3.h 602;" d -SNDBDS_MODE_RESET tg3.h 601;" d -SNDBDS_SEL_CON_IDX_0 tg3.h 608;" d -SNDBDS_SEL_CON_IDX_1 tg3.h 609;" d -SNDBDS_SEL_CON_IDX_10 tg3.h 618;" d -SNDBDS_SEL_CON_IDX_11 tg3.h 619;" d -SNDBDS_SEL_CON_IDX_12 tg3.h 620;" d -SNDBDS_SEL_CON_IDX_13 tg3.h 621;" d -SNDBDS_SEL_CON_IDX_14 tg3.h 622;" d -SNDBDS_SEL_CON_IDX_15 tg3.h 623;" d -SNDBDS_SEL_CON_IDX_2 tg3.h 610;" d -SNDBDS_SEL_CON_IDX_3 tg3.h 611;" d -SNDBDS_SEL_CON_IDX_4 tg3.h 612;" d -SNDBDS_SEL_CON_IDX_5 tg3.h 613;" d -SNDBDS_SEL_CON_IDX_6 tg3.h 614;" d -SNDBDS_SEL_CON_IDX_7 tg3.h 615;" d -SNDBDS_SEL_CON_IDX_8 tg3.h 616;" d -SNDBDS_SEL_CON_IDX_9 tg3.h 617;" d -SNDBDS_STATUS tg3.h 604;" d -SNDBDS_STATUS_ERROR_ATTN tg3.h 605;" d -SNDDATAC_MODE tg3.h 594;" d -SNDDATAC_MODE_ENABLE tg3.h 596;" d -SNDDATAC_MODE_RESET tg3.h 595;" d -SNDDATAI_AVOID_INTERRUPTS_CNT tg3.h 589;" d -SNDDATAI_COS_CNT_0 tg3.h 567;" d -SNDDATAI_COS_CNT_1 tg3.h 568;" d -SNDDATAI_COS_CNT_10 tg3.h 577;" d -SNDDATAI_COS_CNT_11 tg3.h 578;" d -SNDDATAI_COS_CNT_12 tg3.h 579;" d -SNDDATAI_COS_CNT_13 tg3.h 580;" d -SNDDATAI_COS_CNT_14 tg3.h 581;" d -SNDDATAI_COS_CNT_15 tg3.h 582;" d -SNDDATAI_COS_CNT_2 tg3.h 569;" d -SNDDATAI_COS_CNT_3 tg3.h 570;" d -SNDDATAI_COS_CNT_4 tg3.h 571;" d -SNDDATAI_COS_CNT_5 tg3.h 572;" d -SNDDATAI_COS_CNT_6 tg3.h 573;" d -SNDDATAI_COS_CNT_7 tg3.h 574;" d -SNDDATAI_COS_CNT_8 tg3.h 575;" d -SNDDATAI_COS_CNT_9 tg3.h 576;" d -SNDDATAI_DMA_PRIO_RDQ_FULL_CNT tg3.h 584;" d -SNDDATAI_DMA_RDQ_FULL_CNT tg3.h 583;" d -SNDDATAI_INTERRUPTS_CNT tg3.h 588;" d -SNDDATAI_MODE tg3.h 552;" d -SNDDATAI_MODE_ENABLE tg3.h 554;" d -SNDDATAI_MODE_RESET tg3.h 553;" d -SNDDATAI_MODE_STAT_OFLOW_ENAB tg3.h 555;" d -SNDDATAI_NICRNG_SSND_PIDX_CNT tg3.h 586;" d -SNDDATAI_SCTRL_CLEAR tg3.h 561;" d -SNDDATAI_SCTRL_ENABLE tg3.h 559;" d -SNDDATAI_SCTRL_FASTUPD tg3.h 560;" d -SNDDATAI_SCTRL_FLUSH tg3.h 562;" d -SNDDATAI_SCTRL_FORCE_ZERO tg3.h 563;" d -SNDDATAI_SDCQ_FULL_CNT tg3.h 585;" d -SNDDATAI_SND_THRESH_HIT_CNT tg3.h 590;" d -SNDDATAI_STATSCTRL tg3.h 558;" d -SNDDATAI_STATSENAB tg3.h 564;" d -SNDDATAI_STATSINCMASK tg3.h 565;" d -SNDDATAI_STATS_UPDATED_CNT tg3.h 587;" d -SNDDATAI_STATUS tg3.h 556;" d -SNDDATAI_STATUS_STAT_OFLOW tg3.h 557;" d -SPEED_INVALID tg3.h 1791;" d -SPLIT_MODE_5704_MAX_REQ tg3.h 1925;" d -SWARB_GNT0 tg3.h 1322;" d -SWARB_GNT1 tg3.h 1323;" d -SWARB_GNT2 tg3.h 1324;" d -SWARB_GNT3 tg3.h 1325;" d -SWARB_REQ0 tg3.h 1326;" d -SWARB_REQ1 tg3.h 1327;" d -SWARB_REQ2 tg3.h 1328;" d -SWARB_REQ3 tg3.h 1329;" d -SWARB_REQ_CLR0 tg3.h 1318;" d -SWARB_REQ_CLR1 tg3.h 1319;" d -SWARB_REQ_CLR2 tg3.h 1320;" d -SWARB_REQ_CLR3 tg3.h 1321;" d -SWARB_REQ_SET0 tg3.h 1314;" d -SWARB_REQ_SET1 tg3.h 1315;" d -SWARB_REQ_SET2 tg3.h 1316;" d -SWARB_REQ_SET3 tg3.h 1317;" d -TEST_BUFFER_SIZE tg3.c 7219;" d file: -TG3PCI_BASE0_HIGH tg3.h 46;" d -TG3PCI_BASE0_LOW tg3.h 45;" d -TG3PCI_BIST tg3.h 44;" d -TG3PCI_BR_SUPP_EXT tg3.h 71;" d -TG3PCI_CACHELINESZ tg3.h 41;" d -TG3PCI_CAPLIST tg3.h 51;" d -TG3PCI_CCREVID tg3.h 40;" d -TG3PCI_CLOCK_CTRL tg3.h 180;" d -TG3PCI_COMMAND tg3.h 38;" d -TG3PCI_DEVICE tg3.h 33;" d -TG3PCI_DEVICE_TIGON3_1 tg3.h 34;" d -TG3PCI_DEVICE_TIGON3_2 tg3.h 35;" d -TG3PCI_DEVICE_TIGON3_3 tg3.h 36;" d -TG3PCI_DEVICE_TIGON3_4 tg3.h 37;" d -TG3PCI_DMA_RW_CTRL tg3.h 138;" d -TG3PCI_HEADERTYPE tg3.h 43;" d -TG3PCI_IRQ_LINE tg3.h 53;" d -TG3PCI_IRQ_PIN tg3.h 54;" d -TG3PCI_LATTIMER tg3.h 42;" d -TG3PCI_MAX_LAT tg3.h 56;" d -TG3PCI_MEM_WIN_BASE_ADDR tg3.h 192;" d -TG3PCI_MEM_WIN_DATA tg3.h 194;" d -TG3PCI_MIN_GNT tg3.h 55;" d -TG3PCI_MISC_CFG tg3.h 196;" d -TG3PCI_MISC_HOST_CTRL tg3.h 85;" d -TG3PCI_MISC_LOCAL_CTRL tg3.h 197;" d -TG3PCI_MODE_CTRL tg3.h 195;" d -TG3PCI_MSI_ADDR_HIGH tg3.h 82;" d -TG3PCI_MSI_ADDR_LOW tg3.h 81;" d -TG3PCI_MSI_CAP_ID tg3.h 78;" d -TG3PCI_MSI_CAP_PTR tg3.h 74;" d -TG3PCI_MSI_CTRL tg3.h 80;" d -TG3PCI_MSI_DATA tg3.h 83;" d -TG3PCI_NXT_CAP_PTR tg3.h 79;" d -TG3PCI_PCISTATE tg3.h 170;" d -TG3PCI_PM_CAPS tg3.h 69;" d -TG3PCI_PM_CAP_ID tg3.h 67;" d -TG3PCI_PM_CAP_PTR tg3.h 64;" d -TG3PCI_PM_CTRL_STAT tg3.h 70;" d -TG3PCI_PM_DATA tg3.h 72;" d -TG3PCI_RCV_RET_RING_CON_IDX tg3.h 200;" d -TG3PCI_REG_BASE_ADDR tg3.h 191;" d -TG3PCI_REG_DATA tg3.h 193;" d -TG3PCI_ROMADDR tg3.h 50;" d -TG3PCI_SND_PROD_IDX tg3.h 201;" d -TG3PCI_STATUS tg3.h 39;" d -TG3PCI_STD_RING_PROD_IDX tg3.h 199;" d -TG3PCI_SUBSYSID tg3.h 49;" d -TG3PCI_SUBSYSVENID tg3.h 48;" d -TG3PCI_VENDOR tg3.h 31;" d -TG3PCI_VENDOR_BROADCOM tg3.h 32;" d -TG3PCI_VPD_ADDR_FLAG tg3.h 75;" d -TG3PCI_VPD_CAP_ID tg3.h 73;" d -TG3PCI_VPD_CAP_PTR tg3.h 68;" d -TG3PCI_VPD_DATA tg3.h 77;" d -TG3PCI_X_CAPS tg3.h 57;" d -TG3PCI_X_COMMAND tg3.h 65;" d -TG3PCI_X_STATUS tg3.h 66;" d -TG3_64BIT_REG_HIGH tg3.h 11;" d -TG3_64BIT_REG_LOW tg3.h 12;" d -TG3_BDINFO_HOST_ADDR tg3.h 15;" d -TG3_BDINFO_MAXLEN_FLAGS tg3.h 16;" d -TG3_BDINFO_NIC_ADDR tg3.h 21;" d -TG3_BDINFO_SIZE tg3.h 22;" d -TG3_BMCR_SPEED1000 tg3.h 1412;" d -TG3_DEF_MAC_MODE tg3.c 62;" d file: -TG3_DEF_MSG_ENABLE tg3.c 65;" d file: -TG3_DEF_RX_JUMBO_RING_PENDING tg3.c 92;" d file: -TG3_DEF_RX_MODE tg3.c 63;" d file: -TG3_DEF_RX_RING_PENDING tg3.c 90;" d file: -TG3_DEF_TX_MODE tg3.c 64;" d file: -TG3_DEF_TX_RING_PENDING tg3.c 105;" d file: -TG3_FLAG_10_100_ONLY tg3.h 1908;" d -TG3_FLAG_5701_REG_WRITE_BUG tg3.h 1890;" d -TG3_FLAG_BROKEN_CHECKSUMS tg3.h 1912;" d -TG3_FLAG_EEPROM_WRITE_PROT tg3.h 1896;" d -TG3_FLAG_ENABLE_ASF tg3.h 1889;" d -TG3_FLAG_GOT_SERDES_FLOWCTL tg3.h 1913;" d -TG3_FLAG_HOST_TXDS tg3.h 1884;" d -TG3_FLAG_INIT_COMPLETE tg3.h 1915;" d -TG3_FLAG_JUMBO_ENABLE tg3.h 1907;" d -TG3_FLAG_MBOX_WRITE_REORDER tg3.h 1892;" d -TG3_FLAG_NO_RX_PSEUDO_CSUM tg3.h 1905;" d -TG3_FLAG_NO_TX_PSEUDO_CSUM tg3.h 1904;" d -TG3_FLAG_NVRAM tg3.h 1897;" d -TG3_FLAG_NVRAM_BUFFERED tg3.h 1898;" d -TG3_FLAG_PAUSE_AUTONEG tg3.h 1909;" d -TG3_FLAG_PAUSE_RX tg3.h 1910;" d -TG3_FLAG_PAUSE_TX tg3.h 1911;" d -TG3_FLAG_PCIX_MODE tg3.h 1901;" d -TG3_FLAG_PCIX_TARGET_HWBUG tg3.h 1893;" d -TG3_FLAG_PCI_32BIT tg3.h 1903;" d -TG3_FLAG_PCI_HIGH_SPEED tg3.h 1902;" d -TG3_FLAG_POLL_SERDES tg3.h 1891;" d -TG3_FLAG_RX_CHECKSUMS tg3.h 1886;" d -TG3_FLAG_RX_PAUSE tg3.h 1899;" d -TG3_FLAG_SERDES_WOL_CAP tg3.h 1906;" d -TG3_FLAG_SPLIT_MODE tg3.h 1914;" d -TG3_FLAG_TXD_MBOX_HWBUG tg3.h 1885;" d -TG3_FLAG_TX_PAUSE tg3.h 1900;" d -TG3_FLAG_USE_LINKCHG_REG tg3.h 1887;" d -TG3_FLAG_USE_MI_INTERRUPT tg3.h 1888;" d -TG3_FLAG_WOL_ENABLE tg3.h 1895;" d -TG3_FLAG_WOL_SPEED_100MB tg3.h 1894;" d -TG3_FLG2_IS_5788 tg3.h 1920;" d -TG3_FLG2_MAX_RXPEND_64 tg3.h 1921;" d -TG3_FLG2_NO_ETH_WIRE_SPEED tg3.h 1919;" d -TG3_FLG2_RESTART_TIMER tg3.h 1917;" d -TG3_FLG2_SUN_5704 tg3.h 1918;" d -TG3_FLG2_TSO_CAPABLE tg3.h 1922;" d -TG3_FW_BSS_ADDR tg3.c 3569;" d file: -TG3_FW_BSS_LEN tg3.c 3570;" d file: -TG3_FW_DATA_ADDR tg3.c 3565;" d file: -TG3_FW_DATA_LEN tg3.c 3566;" d file: -TG3_FW_RELASE_MINOR tg3.c 3558;" d file: -TG3_FW_RELEASE_FIX tg3.c 3559;" d file: -TG3_FW_RELEASE_MAJOR tg3.c 3557;" d file: -TG3_FW_RODATA_ADDR tg3.c 3563;" d file: -TG3_FW_RODATA_LEN tg3.c 3564;" d file: -TG3_FW_SBSS_ADDR tg3.c 3567;" d file: -TG3_FW_SBSS_LEN tg3.c 3568;" d file: -TG3_FW_START_ADDR tg3.c 3560;" d file: -TG3_FW_TEXT_ADDR tg3.c 3561;" d file: -TG3_FW_TEXT_LEN tg3.c 3562;" d file: -TG3_HW_STATUS_SIZE tg3.h 1618;" d -TG3_MAX_MTU tg3.c 82;" d file: -TG3_MIN_MTU tg3.c 81;" d file: -TG3_REGDUMP_LEN tg3.c 5824;" d file: -TG3_RX_JUMBO_RING_BYTES tg3.c 109;" d file: -TG3_RX_JUMBO_RING_SIZE tg3.c 91;" d file: -TG3_RX_RCB_RING_BYTES tg3.c 111;" d file: -TG3_RX_RCB_RING_SIZE tg3.c 100;" d file: -TG3_RX_RING_BYTES tg3.c 107;" d file: -TG3_RX_RING_SIZE tg3.c 89;" d file: -TG3_STAT_ADD32 tg3.c 5149;" d file: -TG3_TSO5_FW_BSS_ADDR tg3.c 4194;" d file: -TG3_TSO5_FW_BSS_LEN tg3.c 4195;" d file: -TG3_TSO5_FW_DATA_ADDR tg3.c 4190;" d file: -TG3_TSO5_FW_DATA_LEN tg3.c 4191;" d file: -TG3_TSO5_FW_RELASE_MINOR tg3.c 4183;" d file: -TG3_TSO5_FW_RELEASE_FIX tg3.c 4184;" d file: -TG3_TSO5_FW_RELEASE_MAJOR tg3.c 4182;" d file: -TG3_TSO5_FW_RODATA_ADDR tg3.c 4188;" d file: -TG3_TSO5_FW_RODATA_LEN tg3.c 4189;" d file: -TG3_TSO5_FW_SBSS_ADDR tg3.c 4192;" d file: -TG3_TSO5_FW_SBSS_LEN tg3.c 4193;" d file: -TG3_TSO5_FW_START_ADDR tg3.c 4185;" d file: -TG3_TSO5_FW_TEXT_ADDR tg3.c 4186;" d file: -TG3_TSO5_FW_TEXT_LEN tg3.c 4187;" d file: -TG3_TSO_FW_BSS_ADDR tg3.c 3874;" d file: -TG3_TSO_FW_BSS_LEN tg3.c 3875;" d file: -TG3_TSO_FW_DATA_ADDR tg3.c 3870;" d file: -TG3_TSO_FW_DATA_LEN tg3.c 3871;" d file: -TG3_TSO_FW_RELASE_MINOR tg3.c 3863;" d file: -TG3_TSO_FW_RELEASE_FIX tg3.c 3864;" d file: -TG3_TSO_FW_RELEASE_MAJOR tg3.c 3862;" d file: -TG3_TSO_FW_RODATA_ADDR tg3.c 3868;" d file: -TG3_TSO_FW_RODATA_LEN tg3.c 3869;" d file: -TG3_TSO_FW_SBSS_ADDR tg3.c 3872;" d file: -TG3_TSO_FW_SBSS_LEN tg3.c 3873;" d file: -TG3_TSO_FW_START_ADDR tg3.c 3865;" d file: -TG3_TSO_FW_TEXT_ADDR tg3.c 3866;" d file: -TG3_TSO_FW_TEXT_LEN tg3.c 3867;" d file: -TG3_TSO_SUPPORT tg3.c 50;" d file: -TG3_TSO_SUPPORT tg3.c 52;" d file: -TG3_TX_RING_BYTES tg3.c 113;" d file: -TG3_TX_RING_SIZE tg3.c 104;" d file: -TG3_TX_TIMEOUT tg3.c 78;" d file: -TG3_TX_WAKEUP_THRESH tg3.c 127;" d file: -TG3_VLAN_TAG_USED tg3.c 44;" d file: -TG3_VLAN_TAG_USED tg3.c 46;" d file: -TXD_ADDR tg3.h 1527;" d -TXD_FLAG_ADD_SRC_ADDR tg3.h 1517;" d -TXD_FLAG_CHOOSE_SRC_ADDR tg3.h 1518;" d -TXD_FLAG_COAL_NOW tg3.h 1514;" d -TXD_FLAG_CPU_POST_DMA tg3.h 1516;" d -TXD_FLAG_CPU_PRE_DMA tg3.h 1515;" d -TXD_FLAG_END tg3.h 1510;" d -TXD_FLAG_IP_CSUM tg3.h 1509;" d -TXD_FLAG_IP_FRAG tg3.h 1511;" d -TXD_FLAG_IP_FRAG_END tg3.h 1512;" d -TXD_FLAG_NO_CRC tg3.h 1519;" d -TXD_FLAG_TCPUDP_CSUM tg3.h 1508;" d -TXD_FLAG_VLAN tg3.h 1513;" d -TXD_LEN_FLAGS tg3.h 1528;" d -TXD_LEN_SHIFT tg3.h 1520;" d -TXD_MSS_SHIFT tg3.h 1524;" d -TXD_SIZE tg3.h 1530;" d -TXD_VLAN_TAG tg3.h 1529;" d -TXD_VLAN_TAG_SHIFT tg3.h 1523;" d -TX_AUTO_NEG_MASK tg3.h 364;" d -TX_AUTO_NEG_SHIFT tg3.h 365;" d -TX_BACKOFF_SEED_MASK tg3.h 356;" d -TX_BUFFS_AVAIL tg3.c 117;" d file: -TX_CPU_BASE tg3.h 1031;" d -TX_CPU_SCRATCH_BASE tg3.c 3683;" d file: -TX_CPU_SCRATCH_SIZE tg3.c 3684;" d file: -TX_LENGTHS_IPG_CRS_MASK tg3.h 409;" d -TX_LENGTHS_IPG_CRS_SHIFT tg3.h 410;" d -TX_LENGTHS_IPG_MASK tg3.h 407;" d -TX_LENGTHS_IPG_SHIFT tg3.h 408;" d -TX_LENGTHS_SLOT_TIME_MASK tg3.h 405;" d -TX_LENGTHS_SLOT_TIME_SHIFT tg3.h 406;" d -TX_MODE_BIG_BCKOFF_ENABLE tg3.h 395;" d -TX_MODE_ENABLE tg3.h 393;" d -TX_MODE_FLOW_CTRL_ENABLE tg3.h 394;" d -TX_MODE_LONG_PAUSE_ENABLE tg3.h 396;" d -TX_MODE_RESET tg3.h 392;" d -TX_RING_GAP tg3.c 115;" d file: -TX_STATUS_LINK_UP tg3.h 401;" d -TX_STATUS_ODI_OVERRUN tg3.h 403;" d -TX_STATUS_ODI_UNDERRUN tg3.h 402;" d -TX_STATUS_SENT_XOFF tg3.h 399;" d -TX_STATUS_SENT_XON tg3.h 400;" d -TX_STATUS_XOFFED tg3.h 398;" d -VPD_ADDR_FLAG_WRITE tg3.h 76;" d -WDMAC_MODE tg3.h 954;" d -WDMAC_MODE_ADDROFLOW_ENAB tg3.h 960;" d -WDMAC_MODE_ENABLE tg3.h 956;" d -WDMAC_MODE_FIFOOFLOW_ENAB tg3.h 961;" d -WDMAC_MODE_FIFOOREAD_ENAB tg3.h 963;" d -WDMAC_MODE_FIFOURUN_ENAB tg3.h 962;" d -WDMAC_MODE_LNGREAD_ENAB tg3.h 964;" d -WDMAC_MODE_MSTABORT_ENAB tg3.h 958;" d -WDMAC_MODE_PARITYERR_ENAB tg3.h 959;" d -WDMAC_MODE_RESET tg3.h 955;" d -WDMAC_MODE_RX_ACCEL tg3.h 965;" d -WDMAC_MODE_TGTABORT_ENAB tg3.h 957;" d -WDMAC_STATUS tg3.h 966;" d -WDMAC_STATUS_ADDROFLOW tg3.h 970;" d -WDMAC_STATUS_FIFOOFLOW tg3.h 971;" d -WDMAC_STATUS_FIFOOREAD tg3.h 973;" d -WDMAC_STATUS_FIFOURUN tg3.h 972;" d -WDMAC_STATUS_LNGREAD tg3.h 974;" d -WDMAC_STATUS_MSTABORT tg3.h 968;" d -WDMAC_STATUS_PARITYERR tg3.h 969;" d -WDMAC_STATUS_TGTABORT tg3.h 967;" d -_T3_H tg3.h 9;" d -__GET_REG32 tg3.c 5844;" d file: -__GET_REG32 tg3.c 5887;" d file: -__cookie1 tg3.h /^ u32 __cookie1;$/;" m struct:tg3_internal_buffer_desc -__cookie2 tg3.h /^ u32 __cookie2;$/;" m struct:tg3_internal_buffer_desc -__cookie3 tg3.h /^ u32 __cookie3;$/;" m struct:tg3_internal_buffer_desc -__devinitdata tg3.c /^static char version[] __devinitdata =$/;" v file: -__reserved0 tg3.h /^ u8 __reserved0[0x400-0x300];$/;" m struct:tg3_hw_stats -__reserved1 tg3.h /^ u64 __reserved1;$/;" m struct:tg3_hw_stats -__reserved2 tg3.h /^ u64 __reserved2;$/;" m struct:tg3_hw_stats -__reserved3 tg3.h /^ u64 __reserved3;$/;" m struct:tg3_hw_stats -__reserved4 tg3.h /^ u8 __reserved4[0xb00-0x9c0];$/;" m struct:tg3_hw_stats -__tg3_set_mac_addr tg3.c /^static void __tg3_set_mac_addr(struct tg3 *tp)$/;" f file: -__tg3_set_rx_mode tg3.c /^static void __tg3_set_rx_mode(struct net_device *dev)$/;" f file: -__unused0 tg3.h /^ u64 __unused0[37];$/;" m struct:tg3_hw_stats -__unused1 tg3.h /^ u64 __unused1[31];$/;" m struct:tg3_hw_stats -__unused2 tg3.h /^ u64 __unused2[9];$/;" m struct:tg3_hw_stats -ability_match tg3.c /^ char ability_match, idle_match, ack_match;$/;" m struct:tg3_fiber_aneginfo file: -ability_match_cfg tg3.c /^ u32 ability_match_cfg;$/;" m struct:tg3_fiber_aneginfo file: -ability_match_count tg3.c /^ int ability_match_count;$/;" m struct:tg3_fiber_aneginfo file: -ack_match tg3.c /^ char ability_match, idle_match, ack_match;$/;" m struct:tg3_fiber_aneginfo file: -active_duplex tg3.h /^ u8 active_duplex;$/;" m struct:tg3_link_config -active_speed tg3.h /^ u16 active_speed;$/;" m struct:tg3_link_config -addr_hi tg3.h /^ u32 addr_hi;$/;" m struct:tg3_ext_rx_buffer_desc:: -addr_hi tg3.h /^ u32 addr_hi;$/;" m struct:tg3_internal_buffer_desc -addr_hi tg3.h /^ u32 addr_hi;$/;" m struct:tg3_rx_buffer_desc -addr_hi tg3.h /^ u32 addr_hi;$/;" m struct:tg3_tx_buffer_desc -addr_lo tg3.h /^ u32 addr_lo;$/;" m struct:tg3_ext_rx_buffer_desc:: -addr_lo tg3.h /^ u32 addr_lo;$/;" m struct:tg3_internal_buffer_desc -addr_lo tg3.h /^ u32 addr_lo;$/;" m struct:tg3_rx_buffer_desc -addr_lo tg3.h /^ u32 addr_lo;$/;" m struct:tg3_tx_buffer_desc -addrlist tg3.h /^ } addrlist[3];$/;" m struct:tg3_ext_rx_buffer_desc -advertising tg3.h /^ u32 advertising;$/;" m struct:tg3_link_config -asf_counter tg3.h /^ u16 asf_counter;$/;" m struct:tg3 -asf_multiplier tg3.h /^ u16 asf_multiplier;$/;" m struct:tg3 -autoneg tg3.h /^ u8 autoneg;$/;" m struct:tg3_link_config -board_part_number tg3.h /^ char board_part_number[24];$/;" m struct:tg3 -bufmgr_config tg3.h /^ struct tg3_bufmgr_config bufmgr_config;$/;" m struct:tg3 -calc_crc tg3.c /^static inline u32 calc_crc(unsigned char *buf, int len)$/;" f file: -calc_crc_errors tg3.c /^static unsigned long calc_crc_errors(struct tg3 *tp)$/;" f file: -coalesce_mode tg3.h /^ u32 coalesce_mode;$/;" m struct:tg3 -cqid_sqid tg3.h /^ u16 cqid_sqid;$/;" m struct:tg3_internal_buffer_desc -cur_time tg3.c /^ unsigned long link_time, cur_time;$/;" m struct:tg3_fiber_aneginfo file: -data_base tg3.c /^ unsigned int data_base;$/;" m struct:fw_info file: -data_data tg3.c /^ u32 *data_data;$/;" m struct:fw_info file: -data_len tg3.c /^ unsigned int data_len;$/;" m struct:fw_info file: -dev tg3.h /^ struct net_device *dev;$/;" m struct:tg3 -dma_high_water tg3.h /^ u32 dma_high_water;$/;" m struct:tg3_bufmgr_config -dma_low_water tg3.h /^ u32 dma_low_water;$/;" m struct:tg3_bufmgr_config -dma_read_prioq_full tg3.h /^ tg3_stat64_t dma_read_prioq_full;$/;" m struct:tg3_hw_stats -dma_readq_full tg3.h /^ tg3_stat64_t dma_readq_full;$/;" m struct:tg3_hw_stats -dma_rwctrl tg3.h /^ u32 dma_rwctrl;$/;" m struct:tg3 -dma_write_prioq_full tg3.h /^ tg3_stat64_t dma_write_prioq_full;$/;" m struct:tg3_hw_stats -dma_writeq_full tg3.h /^ tg3_stat64_t dma_writeq_full;$/;" m struct:tg3_hw_stats -duplex tg3.h /^ u8 duplex;$/;" m struct:tg3_link_config -err_vlan tg3.h /^ u32 err_vlan;$/;" m struct:tg3_rx_buffer_desc -flags tg3.c /^ u32 flags;$/;" m struct:tg3_fiber_aneginfo file: -flags tg3.h /^ u32 flags;$/;" m struct:tg3_config_info -flags tg3.h /^ u32 flags;$/;" m struct:tg3_internal_buffer_desc -fw_info tg3.c /^struct fw_info {$/;" s file: -get_stat64 tg3.c /^static inline unsigned long get_stat64(tg3_stat64_t *val)$/;" f file: -grc_local_ctrl tg3.h /^ u32 grc_local_ctrl;$/;" m struct:tg3 -grc_mode tg3.h /^ u32 grc_mode;$/;" m struct:tg3 -high tg3.h /^ u32 high, low;$/;" m struct: -hw_stats tg3.h /^ struct tg3_hw_stats *hw_stats;$/;" m struct:tg3 -hw_status tg3.h /^ struct tg3_hw_status *hw_status;$/;" m struct:tg3 -idle_match tg3.c /^ char ability_match, idle_match, ack_match;$/;" m struct:tg3_fiber_aneginfo file: -idx tg3.h /^ } idx[16];$/;" m struct:tg3_hw_status -idx_len tg3.h /^ u32 idx_len;$/;" m struct:tg3_rx_buffer_desc -indirect_lock tg3.h /^ spinlock_t indirect_lock;$/;" m struct:tg3 -ip_tcp_csum tg3.h /^ u32 ip_tcp_csum;$/;" m struct:tg3_rx_buffer_desc -led_mode tg3.h /^ enum phy_led_mode led_mode;$/;" m struct:tg3 -led_mode_auto tg3.h /^ led_mode_auto,$/;" e enum:phy_led_mode -led_mode_link10 tg3.h /^ led_mode_link10$/;" e enum:phy_led_mode -led_mode_three_link tg3.h /^ led_mode_three_link,$/;" e enum:phy_led_mode -len tg3.h /^ u16 len;$/;" m struct:tg3_internal_buffer_desc -len2_len1 tg3.h /^ u32 len2_len1;$/;" m struct:tg3_ext_rx_buffer_desc -len_flags tg3.h /^ u32 len_flags;$/;" m struct:tg3_tx_buffer_desc -link_config tg3.h /^ struct tg3_link_config link_config;$/;" m struct:tg3 -link_time tg3.c /^ unsigned long link_time, cur_time;$/;" m struct:tg3_fiber_aneginfo file: -lock tg3.h /^ spinlock_t lock;$/;" m struct:tg3 -low tg3.h /^ u32 high, low;$/;" m struct: -mac_mode tg3.h /^ u32 mac_mode;$/;" m struct:tg3 -mbuf_high_water tg3.h /^ u32 mbuf_high_water;$/;" m struct:tg3_bufmgr_config -mbuf_high_water_jumbo tg3.h /^ u32 mbuf_high_water_jumbo;$/;" m struct:tg3_bufmgr_config -mbuf_mac_rx_low_water tg3.h /^ u32 mbuf_mac_rx_low_water;$/;" m struct:tg3_bufmgr_config -mbuf_mac_rx_low_water_jumbo tg3.h /^ u32 mbuf_mac_rx_low_water_jumbo;$/;" m struct:tg3_bufmgr_config -mbuf_read_dma_low_water tg3.h /^ u32 mbuf_read_dma_low_water;$/;" m struct:tg3_bufmgr_config -mbuf_read_dma_low_water_jumbo tg3.h /^ u32 mbuf_read_dma_low_water_jumbo;$/;" m struct:tg3_bufmgr_config -mi_mode tg3.h /^ u32 mi_mode;$/;" m struct:tg3 -misc_host_ctrl tg3.h /^ u32 misc_host_ctrl;$/;" m struct:tg3 -msg_enable tg3.h /^ u32 msg_enable;$/;" m struct:tg3 -net_stats tg3.h /^ struct net_device_stats net_stats;$/;" m struct:tg3 -net_stats_prev tg3.h /^ struct net_device_stats net_stats_prev;$/;" m struct:tg3 -nic_avoided_irqs tg3.h /^ tg3_stat64_t nic_avoided_irqs;$/;" m struct:tg3_hw_stats -nic_irqs tg3.h /^ tg3_stat64_t nic_irqs;$/;" m struct:tg3_hw_stats -nic_mbuf tg3.h /^ u32 nic_mbuf;$/;" m struct:tg3_internal_buffer_desc -nic_sram_data_cfg tg3.h /^ u32 nic_sram_data_cfg;$/;" m struct:tg3 -nic_tx_threshold_hit tg3.h /^ tg3_stat64_t nic_tx_threshold_hit;$/;" m struct:tg3_hw_stats -opaque tg3.h /^ u32 opaque;$/;" m struct:tg3_rx_buffer_desc -orig_autoneg tg3.h /^ u8 orig_autoneg;$/;" m struct:tg3_link_config -orig_duplex tg3.h /^ u8 orig_duplex;$/;" m struct:tg3_link_config -orig_speed tg3.h /^ u16 orig_speed;$/;" m struct:tg3_link_config -pci_bist tg3.h /^ u8 pci_bist;$/;" m struct:tg3 -pci_cacheline_sz tg3.h /^ u8 pci_cacheline_sz;$/;" m struct:tg3 -pci_cfg_state tg3.h /^ u32 pci_cfg_state[64 \/ sizeof(u32)];$/;" m struct:tg3 -pci_chip_rev_id tg3.h /^ u16 pci_chip_rev_id;$/;" m struct:tg3 -pci_clock_ctrl tg3.h /^ u32 pci_clock_ctrl;$/;" m struct:tg3 -pci_hdr_type tg3.h /^ u8 pci_hdr_type;$/;" m struct:tg3 -pci_lat_timer tg3.h /^ u8 pci_lat_timer;$/;" m struct:tg3 -pdev tg3.h /^ struct pci_dev *pdev;$/;" m struct:tg3 -pdev_peer tg3.h /^ struct pci_dev *pdev_peer;$/;" m struct:tg3 -phy_crc_errors tg3.h /^ unsigned long phy_crc_errors;$/;" m struct:tg3 -phy_id tg3.c /^ u32 phy_id;$/;" m struct:subsys_tbl_ent file: -phy_id tg3.h /^ u32 phy_id;$/;" m struct:tg3 -phy_is_low_power tg3.h /^ int phy_is_low_power;$/;" m struct:tg3_link_config -phy_led_mode tg3.h /^enum phy_led_mode {$/;" g -pm_cap tg3.h /^ int pm_cap;$/;" m struct:tg3 -regs tg3.h /^ unsigned long regs;$/;" m struct:tg3 -reserved tg3.h /^ u16 reserved;$/;" m struct:tg3_hw_status -reserved tg3.h /^ u32 reserved;$/;" m struct:tg3_rx_buffer_desc -reset_task tg3.h /^ struct work_struct reset_task;$/;" m struct:tg3 -resv_len3 tg3.h /^ u32 resv_len3;$/;" m struct:tg3_ext_rx_buffer_desc -ring_info tg3.h /^struct ring_info {$/;" s -ring_set_send_prod_index tg3.h /^ tg3_stat64_t ring_set_send_prod_index;$/;" m struct:tg3_hw_stats -ring_status_update tg3.h /^ tg3_stat64_t ring_status_update;$/;" m struct:tg3_hw_stats -rodata_base tg3.c /^ unsigned int rodata_base;$/;" m struct:fw_info file: -rodata_data tg3.c /^ u32 *rodata_data;$/;" m struct:fw_info file: -rodata_len tg3.c /^ unsigned int rodata_len;$/;" m struct:fw_info file: -rx_1024_to_1522_octet_packets tg3.h /^ tg3_stat64_t rx_1024_to_1522_octet_packets;$/;" m struct:tg3_hw_stats -rx_128_to_255_octet_packets tg3.h /^ tg3_stat64_t rx_128_to_255_octet_packets;$/;" m struct:tg3_hw_stats -rx_1523_to_2047_octet_packets tg3.h /^ tg3_stat64_t rx_1523_to_2047_octet_packets;$/;" m struct:tg3_hw_stats -rx_2048_to_4095_octet_packets tg3.h /^ tg3_stat64_t rx_2048_to_4095_octet_packets;$/;" m struct:tg3_hw_stats -rx_256_to_511_octet_packets tg3.h /^ tg3_stat64_t rx_256_to_511_octet_packets;$/;" m struct:tg3_hw_stats -rx_4096_to_8191_octet_packets tg3.h /^ tg3_stat64_t rx_4096_to_8191_octet_packets;$/;" m struct:tg3_hw_stats -rx_512_to_1023_octet_packets tg3.h /^ tg3_stat64_t rx_512_to_1023_octet_packets;$/;" m struct:tg3_hw_stats -rx_64_or_less_octet_packets tg3.h /^ tg3_stat64_t rx_64_or_less_octet_packets;$/;" m struct:tg3_hw_stats -rx_65_to_127_octet_packets tg3.h /^ tg3_stat64_t rx_65_to_127_octet_packets;$/;" m struct:tg3_hw_stats -rx_8192_to_9022_octet_packets tg3.h /^ tg3_stat64_t rx_8192_to_9022_octet_packets;$/;" m struct:tg3_hw_stats -rx_align_errors tg3.h /^ tg3_stat64_t rx_align_errors;$/;" m struct:tg3_hw_stats -rx_bcast_packets tg3.h /^ tg3_stat64_t rx_bcast_packets;$/;" m struct:tg3_hw_stats -rx_consumer tg3.h /^ u16 rx_consumer;$/;" m struct:tg3_hw_status -rx_discards tg3.h /^ tg3_stat64_t rx_discards;$/;" m struct:tg3_hw_stats -rx_errors tg3.h /^ tg3_stat64_t rx_errors;$/;" m struct:tg3_hw_stats -rx_fcs_errors tg3.h /^ tg3_stat64_t rx_fcs_errors;$/;" m struct:tg3_hw_stats -rx_fragments tg3.h /^ tg3_stat64_t rx_fragments;$/;" m struct:tg3_hw_stats -rx_frame_too_long_errors tg3.h /^ tg3_stat64_t rx_frame_too_long_errors;$/;" m struct:tg3_hw_stats -rx_in_length_errors tg3.h /^ tg3_stat64_t rx_in_length_errors;$/;" m struct:tg3_hw_stats -rx_jabbers tg3.h /^ tg3_stat64_t rx_jabbers;$/;" m struct:tg3_hw_stats -rx_jumbo tg3.h /^ struct tg3_rx_buffer_desc *rx_jumbo;$/;" m struct:tg3 -rx_jumbo_buffers tg3.h /^ struct ring_info *rx_jumbo_buffers;$/;" m struct:tg3 -rx_jumbo_consumer tg3.h /^ u16 rx_jumbo_consumer;$/;" m struct:tg3_hw_status -rx_jumbo_mapping tg3.h /^ dma_addr_t rx_jumbo_mapping;$/;" m struct:tg3 -rx_jumbo_pending tg3.h /^ u32 rx_jumbo_pending;$/;" m struct:tg3 -rx_jumbo_ptr tg3.h /^ u32 rx_jumbo_ptr;$/;" m struct:tg3 -rx_mac_ctrl_rcvd tg3.h /^ tg3_stat64_t rx_mac_ctrl_rcvd;$/;" m struct:tg3_hw_stats -rx_mcast_packets tg3.h /^ tg3_stat64_t rx_mcast_packets;$/;" m struct:tg3_hw_stats -rx_mini_consumer tg3.h /^ u16 rx_mini_consumer;$/;" m struct:tg3_hw_status -rx_mode tg3.h /^ u32 rx_mode;$/;" m struct:tg3 -rx_octets tg3.h /^ tg3_stat64_t rx_octets;$/;" m struct:tg3_hw_stats -rx_offset tg3.h /^ u32 rx_offset;$/;" m struct:tg3 -rx_out_length_errors tg3.h /^ tg3_stat64_t rx_out_length_errors;$/;" m struct:tg3_hw_stats -rx_pending tg3.h /^ u32 rx_pending;$/;" m struct:tg3 -rx_producer tg3.h /^ u16 rx_producer;$/;" m struct:tg3_hw_status:: -rx_rcb tg3.h /^ struct tg3_rx_buffer_desc *rx_rcb;$/;" m struct:tg3 -rx_rcb_mapping tg3.h /^ dma_addr_t rx_rcb_mapping;$/;" m struct:tg3 -rx_rcb_ptr tg3.h /^ u32 rx_rcb_ptr;$/;" m struct:tg3 -rx_std tg3.h /^ struct tg3_rx_buffer_desc *rx_std;$/;" m struct:tg3 -rx_std_buffers tg3.h /^ struct ring_info *rx_std_buffers;$/;" m struct:tg3 -rx_std_mapping tg3.h /^ dma_addr_t rx_std_mapping;$/;" m struct:tg3 -rx_std_ptr tg3.h /^ u32 rx_std_ptr;$/;" m struct:tg3 -rx_threshold_hit tg3.h /^ tg3_stat64_t rx_threshold_hit;$/;" m struct:tg3_hw_stats -rx_ucast_packets tg3.h /^ tg3_stat64_t rx_ucast_packets;$/;" m struct:tg3_hw_stats -rx_undersize_packets tg3.h /^ tg3_stat64_t rx_undersize_packets;$/;" m struct:tg3_hw_stats -rx_xoff_entered tg3.h /^ tg3_stat64_t rx_xoff_entered;$/;" m struct:tg3_hw_stats -rx_xoff_pause_rcvd tg3.h /^ tg3_stat64_t rx_xoff_pause_rcvd;$/;" m struct:tg3_hw_stats -rx_xon_pause_rcvd tg3.h /^ tg3_stat64_t rx_xon_pause_rcvd;$/;" m struct:tg3_hw_stats -rxbds_empty tg3.h /^ tg3_stat64_t rxbds_empty;$/;" m struct:tg3_hw_stats -rxconfig tg3.c /^ u32 txconfig, rxconfig;$/;" m struct:tg3_fiber_aneginfo file: -skb tg3.h /^ struct sk_buff *skb;$/;" m struct:ring_info -skb tg3.h /^ struct sk_buff *skb;$/;" m struct:tx_ring_info -speed tg3.h /^ u16 speed;$/;" m struct:tg3_link_config -split_mode_max_reqs tg3.h /^ u32 split_mode_max_reqs;$/;" m struct:tg3 -state tg3.c /^ int state;$/;" m struct:tg3_fiber_aneginfo file: -stats_mapping tg3.h /^ dma_addr_t stats_mapping;$/;" m struct:tg3 -status tg3.h /^ u32 status;$/;" m struct:tg3_hw_status -status_mapping tg3.h /^ dma_addr_t status_mapping;$/;" m struct:tg3 -status_tag tg3.h /^ u32 status_tag;$/;" m struct:tg3_hw_status -std tg3.h /^ struct tg3_rx_buffer_desc std;$/;" m struct:tg3_ext_rx_buffer_desc -subsys_devid tg3.c /^ u16 subsys_vendor, subsys_devid;$/;" m struct:subsys_tbl_ent file: -subsys_id_to_phy_id tg3.c /^static struct subsys_tbl_ent subsys_id_to_phy_id[] = {$/;" v file: -subsys_tbl_ent tg3.c /^struct subsys_tbl_ent {$/;" s file: -subsys_vendor tg3.c /^ u16 subsys_vendor, subsys_devid;$/;" m struct:subsys_tbl_ent file: -text_base tg3.c /^ unsigned int text_base;$/;" m struct:fw_info file: -text_data tg3.c /^ u32 *text_data;$/;" m struct:fw_info file: -text_len tg3.c /^ unsigned int text_len;$/;" m struct:fw_info file: -tg3 tg3.h /^struct tg3 {$/;" s -tg3FwRodata tg3.c /^static u32 tg3FwRodata[(TG3_FW_RODATA_LEN \/ sizeof(u32)) + 1] = {$/;" v file: -tg3FwText tg3.c /^static u32 tg3FwText[(TG3_FW_TEXT_LEN \/ sizeof(u32)) + 1] = {$/;" v file: -tg3Tso5FwData tg3.c /^u32 tg3Tso5FwData[] = {$/;" v -tg3Tso5FwRodata tg3.c /^u32 tg3Tso5FwRodata[] = {$/;" v -tg3Tso5FwText tg3.c /^static u32 tg3Tso5FwText[] = {$/;" v file: -tg3TsoFwRodata tg3.c /^u32 tg3TsoFwRodata[] = {$/;" v -tg3TsoFwText tg3.c /^static u32 tg3TsoFwText[] = {$/;" v file: -tg3_4g_overflow_test tg3.c /^static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)$/;" f file: -tg3_abort_hw tg3.c /^static int tg3_abort_hw(struct tg3 *tp)$/;" f file: -tg3_alloc_consistent tg3.c /^static int tg3_alloc_consistent(struct tg3 *tp)$/;" f file: -tg3_alloc_rx_skb tg3.c /^static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,$/;" f file: -tg3_aux_stat_to_speed_duplex tg3.c /^static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)$/;" f file: -tg3_bmcr_reset tg3.c /^static int tg3_bmcr_reset(struct tg3 *tp)$/;" f file: -tg3_bufmgr_config tg3.h /^struct tg3_bufmgr_config {$/;" s -tg3_change_mtu tg3.c /^static int tg3_change_mtu(struct net_device *dev, int new_mtu)$/;" f file: -tg3_chip_reset tg3.c /^static void tg3_chip_reset(struct tg3 *tp)$/;" f file: -tg3_cleanup tg3.c /^module_exit(tg3_cleanup);$/;" v -tg3_cleanup tg3.c /^static void __exit tg3_cleanup(void)$/;" f file: -tg3_close tg3.c /^static int tg3_close(struct net_device *dev)$/;" f file: -tg3_cond_int tg3.c /^static inline void tg3_cond_int(struct tg3 *tp)$/;" f file: -tg3_config_info tg3.h /^struct tg3_config_info {$/;" s -tg3_debug tg3.c /^static int tg3_debug = -1; \/* -1 == use TG3_DEF_MSG_ENABLE as value *\/$/;" v file: -tg3_disable_ints tg3.c /^static void tg3_disable_ints(struct tg3 *tp)$/;" f file: -tg3_do_test_dma tg3.c /^static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)$/;" f file: -tg3_driver tg3.c /^static struct pci_driver tg3_driver = {$/;" v file: -tg3_enable_ints tg3.c /^static void tg3_enable_ints(struct tg3 *tp)$/;" f file: -tg3_ethtool_ops tg3.c /^static struct ethtool_ops tg3_ethtool_ops = {$/;" v file: -tg3_ext_rx_buffer_desc tg3.h /^struct tg3_ext_rx_buffer_desc {$/;" s -tg3_fiber_aneg_smachine tg3.c /^static int tg3_fiber_aneg_smachine(struct tg3 *tp,$/;" f file: -tg3_fiber_aneginfo tg3.c /^struct tg3_fiber_aneginfo {$/;" s file: -tg3_find_5704_peer tg3.c /^static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)$/;" f file: -tg3_flags tg3.h /^ u32 tg3_flags;$/;" m struct:tg3 -tg3_flags2 tg3.h /^ u32 tg3_flags2;$/;" m struct:tg3 -tg3_free_consistent tg3.c /^static void tg3_free_consistent(struct tg3 *tp)$/;" f file: -tg3_free_rings tg3.c /^static void tg3_free_rings(struct tg3 *tp)$/;" f file: -tg3_frob_aux_power tg3.c /^static void tg3_frob_aux_power(struct tg3 *tp)$/;" f file: -tg3_get_default_macaddr_sparc tg3.c /^static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)$/;" f file: -tg3_get_device_address tg3.c /^static int __devinit tg3_get_device_address(struct tg3 *tp)$/;" f file: -tg3_get_drvinfo tg3.c /^static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)$/;" f file: -tg3_get_invariants tg3.c /^static int __devinit tg3_get_invariants(struct tg3 *tp)$/;" f file: -tg3_get_macaddr_sparc tg3.c /^static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)$/;" f file: -tg3_get_msglevel tg3.c /^static u32 tg3_get_msglevel(struct net_device *dev)$/;" f file: -tg3_get_pauseparam tg3.c /^static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)$/;" f file: -tg3_get_regs tg3.c /^static void tg3_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)$/;" f file: -tg3_get_regs_len tg3.c /^static int tg3_get_regs_len(struct net_device *dev)$/;" f file: -tg3_get_ringparam tg3.c /^static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)$/;" f file: -tg3_get_rx_csum tg3.c /^static u32 tg3_get_rx_csum(struct net_device *dev)$/;" f file: -tg3_get_settings tg3.c /^static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)$/;" f file: -tg3_get_stats tg3.c /^static struct net_device_stats *tg3_get_stats(struct net_device *dev)$/;" f file: -tg3_get_wol tg3.c /^static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)$/;" f file: -tg3_halt tg3.c /^static int tg3_halt(struct tg3 *tp)$/;" f file: -tg3_halt_cpu tg3.c /^static int tg3_halt_cpu(struct tg3 *tp, u32 offset)$/;" f file: -tg3_has_work tg3.c /^static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp)$/;" f file: -tg3_hw_stats tg3.h /^struct tg3_hw_stats {$/;" s -tg3_hw_status tg3.h /^struct tg3_hw_status {$/;" s -tg3_init tg3.c /^module_init(tg3_init);$/;" v -tg3_init tg3.c /^static int __init tg3_init(void)$/;" f file: -tg3_init_5401phy_dsp tg3.c /^static int tg3_init_5401phy_dsp(struct tg3 *tp)$/;" f file: -tg3_init_bufmgr_config tg3.c /^static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)$/;" f file: -tg3_init_hw tg3.c /^static int tg3_init_hw(struct tg3 *tp)$/;" f file: -tg3_init_link_config tg3.c /^static void __devinit tg3_init_link_config(struct tg3 *tp)$/;" f file: -tg3_init_one tg3.c /^static int __devinit tg3_init_one(struct pci_dev *pdev,$/;" f file: -tg3_init_rings tg3.c /^static void tg3_init_rings(struct tg3 *tp)$/;" f file: -tg3_internal_buffer_desc tg3.h /^struct tg3_internal_buffer_desc {$/;" s -tg3_interrupt tg3.c /^static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)$/;" f file: -tg3_ioctl tg3.c /^static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)$/;" f file: -tg3_is_sun_5704 tg3.c /^static int __devinit tg3_is_sun_5704(struct tg3 *tp)$/;" f file: -tg3_link_config tg3.h /^struct tg3_link_config {$/;" s -tg3_link_report tg3.c /^static void tg3_link_report(struct tg3 *tp)$/;" f file: -tg3_load_5701_a0_firmware_fix tg3.c /^static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)$/;" f file: -tg3_load_firmware_cpu tg3.c /^static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,$/;" f file: -tg3_load_tso_firmware tg3.c /^static int tg3_load_tso_firmware(struct tg3 *tp)$/;" f file: -tg3_netif_start tg3.c /^static inline void tg3_netif_start(struct tg3 *tp)$/;" f file: -tg3_netif_stop tg3.c /^static inline void tg3_netif_stop(struct tg3 *tp)$/;" f file: -tg3_nvram_init tg3.c /^static void __devinit tg3_nvram_init(struct tg3 *tp)$/;" f file: -tg3_nvram_read tg3.c /^static int __devinit tg3_nvram_read(struct tg3 *tp,$/;" f file: -tg3_nvram_read_using_eeprom tg3.c /^static int __devinit tg3_nvram_read_using_eeprom(struct tg3 *tp,$/;" f file: -tg3_nway_reset tg3.c /^static int tg3_nway_reset(struct net_device *dev)$/;" f file: -tg3_open tg3.c /^static int tg3_open(struct net_device *dev)$/;" f file: -tg3_pci_tbl tg3.c /^static struct pci_device_id tg3_pci_tbl[] = {$/;" v file: -tg3_periodic_fetch_stats tg3.c /^static void tg3_periodic_fetch_stats(struct tg3 *tp)$/;" f file: -tg3_phy_copper_begin tg3.c /^static int tg3_phy_copper_begin(struct tg3 *tp, int wait_for_link)$/;" f file: -tg3_phy_probe tg3.c /^static int __devinit tg3_phy_probe(struct tg3 *tp)$/;" f file: -tg3_phy_reset tg3.c /^static int tg3_phy_reset(struct tg3 *tp, int force)$/;" f file: -tg3_phy_reset_5703_4_5 tg3.c /^static int tg3_phy_reset_5703_4_5(struct tg3 *tp)$/;" f file: -tg3_phy_reset_chanpat tg3.c /^static int tg3_phy_reset_chanpat(struct tg3 *tp)$/;" f file: -tg3_phy_set_wirespeed tg3.c /^static void tg3_phy_set_wirespeed(struct tg3 *tp)$/;" f file: -tg3_phy_string tg3.c /^static char * __devinit tg3_phy_string(struct tg3 *tp)$/;" f file: -tg3_phy_write_and_check_testpat tg3.c /^static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)$/;" f file: -tg3_poll tg3.c /^static int tg3_poll(struct net_device *netdev, int *budget)$/;" f file: -tg3_read_mem tg3.c /^static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)$/;" f file: -tg3_read_partno tg3.c /^static void __devinit tg3_read_partno(struct tg3 *tp)$/;" f file: -tg3_readphy tg3.c /^static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)$/;" f file: -tg3_recycle_rx tg3.c /^static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,$/;" f file: -tg3_remove_one tg3.c /^static void __devexit tg3_remove_one(struct pci_dev *pdev)$/;" f file: -tg3_reset_hw tg3.c /^static int tg3_reset_hw(struct tg3 *tp)$/;" f file: -tg3_reset_task tg3.c /^static void tg3_reset_task(void *_data)$/;" f file: -tg3_resume tg3.c /^static int tg3_resume(struct pci_dev *pdev)$/;" f file: -tg3_rx tg3.c /^static int tg3_rx(struct tg3 *tp, int budget)$/;" f file: -tg3_rx_buffer_desc tg3.h /^struct tg3_rx_buffer_desc {$/;" s -tg3_set_bdinfo tg3.c /^static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,$/;" f file: -tg3_set_mac_addr tg3.c /^static int tg3_set_mac_addr(struct net_device *dev, void *p)$/;" f file: -tg3_set_msglevel tg3.c /^static void tg3_set_msglevel(struct net_device *dev, u32 value)$/;" f file: -tg3_set_mtu tg3.c /^static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,$/;" f file: -tg3_set_multi tg3.c /^static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)$/;" f file: -tg3_set_pauseparam tg3.c /^static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)$/;" f file: -tg3_set_power_state tg3.c /^static int tg3_set_power_state(struct tg3 *tp, int state)$/;" f file: -tg3_set_ringparam tg3.c /^static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)$/;" f file: -tg3_set_rx_csum tg3.c /^static int tg3_set_rx_csum(struct net_device *dev, u32 data)$/;" f file: -tg3_set_rx_mode tg3.c /^static void tg3_set_rx_mode(struct net_device *dev)$/;" f file: -tg3_set_settings tg3.c /^static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)$/;" f file: -tg3_set_tso tg3.c /^static int tg3_set_tso(struct net_device *dev, u32 value)$/;" f file: -tg3_set_tx_csum tg3.c /^static int tg3_set_tx_csum(struct net_device *dev, u32 data)$/;" f file: -tg3_set_txd tg3.c /^static void tg3_set_txd(struct tg3 *tp, int entry,$/;" f file: -tg3_set_wol tg3.c /^static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)$/;" f file: -tg3_setup_copper_phy tg3.c /^static int tg3_setup_copper_phy(struct tg3 *tp)$/;" f file: -tg3_setup_fiber_phy tg3.c /^static int tg3_setup_fiber_phy(struct tg3 *tp)$/;" f file: -tg3_setup_flow_control tg3.c /^static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)$/;" f file: -tg3_setup_phy tg3.c /^static int tg3_setup_phy(struct tg3 *tp)$/;" f file: -tg3_start_xmit tg3.c /^static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)$/;" f file: -tg3_start_xmit_4gbug tg3.c /^static int tg3_start_xmit_4gbug(struct sk_buff *skb, struct net_device *dev)$/;" f file: -tg3_stat64_t tg3.h /^} tg3_stat64_t;$/;" t -tg3_stop_block tg3.c /^static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)$/;" f file: -tg3_stop_fw tg3.c /^static void tg3_stop_fw(struct tg3 *tp)$/;" f file: -tg3_suspend tg3.c /^static int tg3_suspend(struct pci_dev *pdev, u32 state)$/;" f file: -tg3_switch_clocks tg3.c /^static void tg3_switch_clocks(struct tg3 *tp)$/;" f file: -tg3_test_dma tg3.c /^static int __devinit tg3_test_dma(struct tg3 *tp)$/;" f file: -tg3_timer tg3.c /^static void tg3_timer(unsigned long __opaque)$/;" f file: -tg3_tx tg3.c /^static void tg3_tx(struct tg3 *tp)$/;" f file: -tg3_tx_buffer_desc tg3.h /^struct tg3_tx_buffer_desc {$/;" s -tg3_tx_timeout tg3.c /^static void tg3_tx_timeout(struct net_device *dev)$/;" f file: -tg3_vlan_rx tg3.c /^static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)$/;" f file: -tg3_vlan_rx_kill_vid tg3.c /^static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)$/;" f file: -tg3_vlan_rx_register tg3.c /^static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)$/;" f file: -tg3_wait_macro_done tg3.c /^static int tg3_wait_macro_done(struct tg3 *tp)$/;" f file: -tg3_write_indirect_reg32 tg3.c /^static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)$/;" f file: -tg3_write_mem tg3.c /^static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)$/;" f file: -tg3_writephy tg3.c /^static int tg3_writephy(struct tg3 *tp, int reg, u32 val)$/;" f file: -tigon3_4gb_hwbug_workaround tg3.c /^static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,$/;" f file: -timer tg3.h /^ struct timer_list timer;$/;" m struct:tg3 -timer_counter tg3.h /^ u16 timer_counter;$/;" m struct:tg3 -timer_multiplier tg3.h /^ u16 timer_multiplier;$/;" m struct:tg3 -timer_offset tg3.h /^ u32 timer_offset;$/;" m struct:tg3 -tr16 tg3.c 217;" d file: -tr32 tg3.c 216;" d file: -tr8 tg3.c 218;" d file: -tw16 tg3.c 214;" d file: -tw32 tg3.c 212;" d file: -tw32_mailbox tg3.c 213;" d file: -tw8 tg3.c 215;" d file: -tx_bcast_packets tg3.h /^ tg3_stat64_t tx_bcast_packets;$/;" m struct:tg3_hw_stats -tx_buffers tg3.h /^ struct tx_ring_info *tx_buffers;$/;" m struct:tg3 -tx_carrier_sense_errors tg3.h /^ tg3_stat64_t tx_carrier_sense_errors;$/;" m struct:tg3_hw_stats -tx_collide_10times tg3.h /^ tg3_stat64_t tx_collide_10times;$/;" m struct:tg3_hw_stats -tx_collide_11times tg3.h /^ tg3_stat64_t tx_collide_11times;$/;" m struct:tg3_hw_stats -tx_collide_12times tg3.h /^ tg3_stat64_t tx_collide_12times;$/;" m struct:tg3_hw_stats -tx_collide_13times tg3.h /^ tg3_stat64_t tx_collide_13times;$/;" m struct:tg3_hw_stats -tx_collide_14times tg3.h /^ tg3_stat64_t tx_collide_14times;$/;" m struct:tg3_hw_stats -tx_collide_15times tg3.h /^ tg3_stat64_t tx_collide_15times;$/;" m struct:tg3_hw_stats -tx_collide_2times tg3.h /^ tg3_stat64_t tx_collide_2times;$/;" m struct:tg3_hw_stats -tx_collide_3times tg3.h /^ tg3_stat64_t tx_collide_3times;$/;" m struct:tg3_hw_stats -tx_collide_4times tg3.h /^ tg3_stat64_t tx_collide_4times;$/;" m struct:tg3_hw_stats -tx_collide_5times tg3.h /^ tg3_stat64_t tx_collide_5times;$/;" m struct:tg3_hw_stats -tx_collide_6times tg3.h /^ tg3_stat64_t tx_collide_6times;$/;" m struct:tg3_hw_stats -tx_collide_7times tg3.h /^ tg3_stat64_t tx_collide_7times;$/;" m struct:tg3_hw_stats -tx_collide_8times tg3.h /^ tg3_stat64_t tx_collide_8times;$/;" m struct:tg3_hw_stats -tx_collide_9times tg3.h /^ tg3_stat64_t tx_collide_9times;$/;" m struct:tg3_hw_stats -tx_collisions tg3.h /^ tg3_stat64_t tx_collisions;$/;" m struct:tg3_hw_stats -tx_comp_queue_full tg3.h /^ tg3_stat64_t tx_comp_queue_full;$/;" m struct:tg3_hw_stats -tx_cons tg3.h /^ u32 tx_cons;$/;" m struct:tg3 -tx_consumer tg3.h /^ u16 tx_consumer;$/;" m struct:tg3_hw_status:: -tx_deferred tg3.h /^ tg3_stat64_t tx_deferred;$/;" m struct:tg3_hw_stats -tx_desc_mapping tg3.h /^ dma_addr_t tx_desc_mapping;$/;" m struct:tg3 -tx_discards tg3.h /^ tg3_stat64_t tx_discards;$/;" m struct:tg3_hw_stats -tx_errors tg3.h /^ tg3_stat64_t tx_errors;$/;" m struct:tg3_hw_stats -tx_excessive_collisions tg3.h /^ tg3_stat64_t tx_excessive_collisions;$/;" m struct:tg3_hw_stats -tx_flow_control tg3.h /^ tg3_stat64_t tx_flow_control;$/;" m struct:tg3_hw_stats -tx_late_collisions tg3.h /^ tg3_stat64_t tx_late_collisions;$/;" m struct:tg3_hw_stats -tx_lock tg3.h /^ spinlock_t tx_lock;$/;" m struct:tg3 -tx_mac_errors tg3.h /^ tg3_stat64_t tx_mac_errors;$/;" m struct:tg3_hw_stats -tx_mcast_packets tg3.h /^ tg3_stat64_t tx_mcast_packets;$/;" m struct:tg3_hw_stats -tx_mode tg3.h /^ u32 tx_mode;$/;" m struct:tg3 -tx_mult_collisions tg3.h /^ tg3_stat64_t tx_mult_collisions;$/;" m struct:tg3_hw_stats -tx_octets tg3.h /^ tg3_stat64_t tx_octets;$/;" m struct:tg3_hw_stats -tx_pending tg3.h /^ u32 tx_pending;$/;" m struct:tg3 -tx_prod tg3.h /^ u32 tx_prod;$/;" m struct:tg3 -tx_ring tg3.h /^ struct tg3_tx_buffer_desc *tx_ring;$/;" m struct:tg3 -tx_ring_info tg3.h /^struct tx_ring_info {$/;" s -tx_single_collisions tg3.h /^ tg3_stat64_t tx_single_collisions;$/;" m struct:tg3_hw_stats -tx_ucast_packets tg3.h /^ tg3_stat64_t tx_ucast_packets;$/;" m struct:tg3_hw_stats -tx_xoff_sent tg3.h /^ tg3_stat64_t tx_xoff_sent;$/;" m struct:tg3_hw_stats -tx_xon_sent tg3.h /^ tg3_stat64_t tx_xon_sent;$/;" m struct:tg3_hw_stats -txconfig tg3.c /^ u32 txconfig, rxconfig;$/;" m struct:tg3_fiber_aneginfo file: -type_flags tg3.h /^ u32 type_flags;$/;" m struct:tg3_rx_buffer_desc -vlan_tag tg3.h /^ u32 vlan_tag;$/;" m struct:tg3_tx_buffer_desc -vlgrp tg3.h /^ struct vlan_group *vlgrp;$/;" m struct:tg3 diff -urN vanilla-linux/include/linux/pci_ids.h vanilla-linux-patch/include/linux/pci_ids.h --- vanilla-linux/include/linux/pci_ids.h 2003-10-26 00:13:29.000000000 +0530 +++ vanilla-linux-patch/include/linux/pci_ids.h 2004-03-15 11:23:43.000000000 +0530 @@ -1817,6 +1817,10 @@ #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea #define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb +#define PCI_VENDOR_ID_S2IO 0x17d5 +#define PCI_DEVICE_ID_S2IO_WIN 0x5731 +#define PCI_DEVICE_ID_S2IO_UNI 0x5831 + #define PCI_VENDOR_ID_SYMPHONY 0x1c1c #define PCI_DEVICE_ID_SYMPHONY_101 0x0001