From mboxrd@z Thu Jan 1 00:00:00 1970 From: Robert Budde Date: Fri, 27 Nov 2009 14:28:22 +0100 Subject: [ath9k-devel] Enabling halfrate (10 MHz bandwidth) on AR9280 and later Message-ID: <002f01ca6f65$7dfd6920$79f83b60$@Budde@gmx.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: ath9k-devel@lists.ath9k.org Hi all, we are trying hard to enable halfrate (10 MHz bw) on the AR9280 chipset. All other pci-devices we have (AR5416 etc.) as well as AR5418 (PCIe) are working fine at 10 MHz bandwidth. Setting the pll of the AR9280 to senseful values such as 0x2828 or 0x5428 results in consecutive tx hangs. Sometimes we are able to rx or tx some frames but operation is very unreliable. Setting the bandwidth to 13 MHz or more allows stable operation. The reliability at a given bandwidth varies with every device which makes us think that the problem is timing-related. We toyed around with that dma-settings as well as the PCIE and workaround-register (AR_WA) but had no luck. Can somebody give us a hint what to look for? Will this problem ever be tackled? The AR9280 product bulletin states that the chipset is conforming IEEE802.11j. This at least means that the chipset should support 10 MHz (halfrate) operation!? Best regards Robert -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.ath9k.org/pipermail/ath9k-devel/attachments/20091127/4e050e0a/attachment.htm