From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sangsu Park Subject: [RESEND][PATCH] ARM: EXYNOS: Add clocks for EXYNOS I2S and PCM I/F Date: Wed, 06 Feb 2013 14:21:02 +0900 Message-ID: <003201ce0429$c15e8350$441b89f0$@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-path: Received: from mailout2.samsung.com ([203.254.224.25]:61816 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751317Ab3BFFVE (ORCPT ); Wed, 6 Feb 2013 00:21:04 -0500 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MHS00MYJ9J03EI0@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 06 Feb 2013 14:21:02 +0900 (KST) Received: from DOSANGSU4UP02 ([12.23.118.226]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MHS00GWI9J2VZ80@mmp2.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 06 Feb 2013 14:21:02 +0900 (KST) Content-language: ko Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: ben-linux@fluff.org, Kukjin Kim , sbkim73@samsung.com, Tushar Behera Audio Subsystem has own clocks for I2S0 and PCM0 in all EXYNOS series. This patch add clocks for I2S0 and PCM0 I/F. Signed-off-by: Sangsu Park --- arch/arm/mach-exynos/Makefile | 1 + arch/arm/mach-exynos/clock-audss.c | 64 ++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-exynos/clock-audss.c diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 7e53a3a..5b6c7c0 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -13,6 +13,7 @@ obj- := # Core obj-$(CONFIG_ARCH_EXYNOS) += common.o +obj-$(CONFIG_ARCH_EXYNOS) += clock-audss.o obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o diff --git a/arch/arm/mach-exynos/clock-audss.c b/arch/arm/mach-exynos/clock-audss.c new file mode 100644 index 0000000..8260185 --- /dev/null +++ b/arch/arm/mach-exynos/clock-audss.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Clock support for EXYNOS Audio Subsystem + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#define EXYNOS_PA_AUDSS (0x03810000) + +/* IP Clock Gate 0 Registers */ +#define EXYNOS_AUDSS_CLKGATE_I2SBUS (1<<2) +#define EXYNOS_AUDSS_CLKGATE_I2SSPECIAL (1<<3) +#define EXYNOS_AUDSS_CLKGATE_PCMBUS (1<<4) +#define EXYNOS_AUDSS_CLKGATE_PCMSPECIAL (1<<5) +#define EXYNOS_AUDSS_CLKGATE_GPIO (1<<6) + +static void __iomem *clk_audss_base = 0; + +static int exynos_clk_audss_ctrl(struct clk *clk, int enable) +{ + if (!clk_audss_base) + return ENOMEM; + + return s5p_gatectrl(clk_audss_base, clk, enable); +} + +static struct clk exynos_init_audss_clocks[] = { + { + .name = "iis", + .devname = "samsung-i2s.0", + .enable = exynos_clk_audss_ctrl, + .ctrlbit = EXYNOS_AUDSS_CLKGATE_I2SSPECIAL | EXYNOS_AUDSS_CLKGATE_I2SBUS + | EXYNOS_AUDSS_CLKGATE_GPIO, + }, { + .name = "pcm", + .devname = "samsung-pcm.0", + .enable = exynos_clk_audss_ctrl, + .ctrlbit = EXYNOS_AUDSS_CLKGATE_PCMSPECIAL | EXYNOS_AUDSS_CLKGATE_PCMBUS + | EXYNOS_AUDSS_CLKGATE_GPIO, + }, +}; + +void __init exynos_register_audss_clocks(void) +{ + clk_audss_base = ioremap(EXYNOS_PA_AUDSS, SZ_4K); + if (clk_audss_base == NULL) { + pr_err("unable to ioremap for gpio_base1\n"); + return; + } + + s3c_register_clocks(exynos_init_audss_clocks, ARRAY_SIZE(exynos_init_audss_clocks)); + s3c_disable_clocks(exynos_init_audss_clocks, ARRAY_SIZE(exynos_init_audss_clocks)); +} -- 1.7.4.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: sangsu4u.park@samsung.com (Sangsu Park) Date: Wed, 06 Feb 2013 14:21:02 +0900 Subject: [RESEND][PATCH] ARM: EXYNOS: Add clocks for EXYNOS I2S and PCM I/F Message-ID: <003201ce0429$c15e8350$441b89f0$@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Audio Subsystem has own clocks for I2S0 and PCM0 in all EXYNOS series. This patch add clocks for I2S0 and PCM0 I/F. Signed-off-by: Sangsu Park --- arch/arm/mach-exynos/Makefile | 1 + arch/arm/mach-exynos/clock-audss.c | 64 ++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-exynos/clock-audss.c diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 7e53a3a..5b6c7c0 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -13,6 +13,7 @@ obj- := # Core obj-$(CONFIG_ARCH_EXYNOS) += common.o +obj-$(CONFIG_ARCH_EXYNOS) += clock-audss.o obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o diff --git a/arch/arm/mach-exynos/clock-audss.c b/arch/arm/mach-exynos/clock-audss.c new file mode 100644 index 0000000..8260185 --- /dev/null +++ b/arch/arm/mach-exynos/clock-audss.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Clock support for EXYNOS Audio Subsystem + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#define EXYNOS_PA_AUDSS (0x03810000) + +/* IP Clock Gate 0 Registers */ +#define EXYNOS_AUDSS_CLKGATE_I2SBUS (1<<2) +#define EXYNOS_AUDSS_CLKGATE_I2SSPECIAL (1<<3) +#define EXYNOS_AUDSS_CLKGATE_PCMBUS (1<<4) +#define EXYNOS_AUDSS_CLKGATE_PCMSPECIAL (1<<5) +#define EXYNOS_AUDSS_CLKGATE_GPIO (1<<6) + +static void __iomem *clk_audss_base = 0; + +static int exynos_clk_audss_ctrl(struct clk *clk, int enable) +{ + if (!clk_audss_base) + return ENOMEM; + + return s5p_gatectrl(clk_audss_base, clk, enable); +} + +static struct clk exynos_init_audss_clocks[] = { + { + .name = "iis", + .devname = "samsung-i2s.0", + .enable = exynos_clk_audss_ctrl, + .ctrlbit = EXYNOS_AUDSS_CLKGATE_I2SSPECIAL | EXYNOS_AUDSS_CLKGATE_I2SBUS + | EXYNOS_AUDSS_CLKGATE_GPIO, + }, { + .name = "pcm", + .devname = "samsung-pcm.0", + .enable = exynos_clk_audss_ctrl, + .ctrlbit = EXYNOS_AUDSS_CLKGATE_PCMSPECIAL | EXYNOS_AUDSS_CLKGATE_PCMBUS + | EXYNOS_AUDSS_CLKGATE_GPIO, + }, +}; + +void __init exynos_register_audss_clocks(void) +{ + clk_audss_base = ioremap(EXYNOS_PA_AUDSS, SZ_4K); + if (clk_audss_base == NULL) { + pr_err("unable to ioremap for gpio_base1\n"); + return; + } + + s3c_register_clocks(exynos_init_audss_clocks, ARRAY_SIZE(exynos_init_audss_clocks)); + s3c_disable_clocks(exynos_init_audss_clocks, ARRAY_SIZE(exynos_init_audss_clocks)); +} -- 1.7.4.1