Re: [PATCH 2/2] iommu/amd-vi: do not zero IOMMU MMIO region

[Jan Beulich <jbeulich@suse.com>]

On 06.05.2026 09:37, Roger Pau Monne wrote:
> @@ -1381,6 +1372,11 @@ static int __init amd_iommu_prepare_one(struct amd_iommu *iommu)
>      if ( amd_iommu_max_paging_mode < amd_iommu_min_paging_mode )
>          return -ERANGE;
>  
> +    /* Read current control register and forcefully disable the IOMMU. */
> +    iommu->ctrl.raw = readq(iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
> +    disable_iommu(iommu, true);

Don't you also need to pre-fill iommu->features? And with that field's use in
disable_iommu(), won't we be at risk of leaving stuff enabled which we are
entirely unaware of? Even if we fully cleared the control register (which
would eliminate the need to fetch features), down the road a 2nd control
register could appear. Has it become clear which register(s) or bit(s) it
really is that are causing the observed issue? IOW is there truly something
we may not clear? Or is it maybe that memset() really isn't suitable for use
against MMIO, especially after having switched to use of REP MOVSB when ERMS
is available?

Jan