From: Andy Pont <andy.pont@sdcsystems.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/4] x86: Document irq router device tree bindings
Date: Wed, 20 May 2015 09:06:41 +0100 [thread overview]
Message-ID: <005501d092d3$edcb9000$c962b000$@pont@sdcsystems.com> (raw)
In-Reply-To: <BLU436-SMTP170F125301E7F0E1B3BF1E2BFC20@phx.gbl>
Hi Bin,
> + "pci": IRQ routing is controlled by PCI configuraiton registers
^^^
One small typo to correct.
Andy.
next prev parent reply other threads:[~2015-05-20 8:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1432108506-32705-1-git-send-email-bmeng.cn@gmail.com>
2015-05-20 7:55 ` [U-Boot] [PATCH 2/4] x86: Document irq router device tree bindings Bin Meng
2015-05-20 8:06 ` Andy Pont [this message]
[not found] ` <555c409e.861b6b0a.1f49.ffffaac0SMTPIN_ADDED_BROKEN@mx.google.com>
2015-05-20 9:06 ` Bin Meng
2015-05-20 17:45 ` Simon Glass
2015-05-20 7:55 ` [U-Boot] [PATCH 3/4] x86: quark: Implement PIRQ routing Bin Meng
2015-05-20 22:20 ` Simon Glass
2015-05-20 7:55 ` [U-Boot] [PATCH 4/4] x86: Do sanity test on pirq table before writing Bin Meng
2015-05-20 22:20 ` Simon Glass
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