diff for duplicates of <006801d62599$d8761690$896243b0$@samsung.com> diff --git a/a/1.txt b/N1/1.txt index 82783fb..a5773b1 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -16,119 +16,126 @@ Hi Rob > > This patch documents Samsung UFS PHY device tree bindings > > > > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> -> > Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>\r -> > ---\r -> > .../bindings/phy/samsung,ufs-phy.yaml | 74 +++++++++++++++++++\r -> > 1 file changed, 74 insertions(+)\r -> > create mode 100644\r -> > Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\r -> >\r -> > diff --git\r -> > a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\r -> > b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\r -> > new file mode 100644\r -> > index 000000000000..352d5dda320d\r -> > --- /dev/null\r -> > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\r -> > @@ -0,0 +1,74 @@\r -> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2\r -> > +---\r -> > +$id:\r -> > +https://protect2.fireeye.com/url?k=5c35df0a-01ffeabd-5c345445-0cc47a3\r -> > +003e8-\r -> aa6c980dab2ba33a&q=1&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2F\r -> > +phy%2Fsamsung%2Cufs-phy.yaml%23\r -> > +$schema:\r -> > +https://protect2.fireeye.com/url?k=9734fc5e-cafec9e9-97357711-0cc47a3\r -> > +003e8-\r -> 79d176b992774339&q=1&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schem\r -> > +as%2Fcore.yaml%23\r -> > +\r -> > +title: Samsung SoC series UFS PHY Device Tree Bindings\r -> > +\r -> > +maintainers:\r -> > + - Alim Akhtar <alim.akhtar@samsung.com>\r -> > +\r -> > +properties:\r -> > + "#phy-cells":\r -> > + const: 0\r -> > +\r -> > + compatible:\r -> > + enum:\r -> > + - samsung,exynos7-ufs-phy\r -> > +\r -> > + reg:\r -> > + maxItems: 1\r -> > + description: PHY base register address\r -> \r -> Can drop the description. Doesn't add anything special.\r -> \r -> > +\r -> > + reg-names:\r -> > + items:\r -> > + - const: phy-pma\r -> > +\r -> > + clocks:\r -> > + items:\r -> > + - description: PLL reference clock\r -> > + - description: symbol clock for input symbol ( rx0-ch0 symbol clock)\r -> > + - description: symbol clock for input symbol ( rx1-ch1 symbol clock)\r -> > + - description: symbol clock for output symbol ( tx0 symbol\r -> > + clock)\r -> > +\r -> > + clock-names:\r -> > + items:\r -> > + - const: ref_clk\r -> > + - const: rx1_symbol_clk\r -> > + - const: rx0_symbol_clk\r -> > + - const: tx0_symbol_clk\r -> > +\r -> > + samsung,pmu-syscon:\r -> > + $ref: '/schemas/types.yaml#/definitions/phandle'\r -> > + description: phandle for PMU system controller interface, used to\r -> > + control pmu registers bits for ufs m-phy\r -> > +\r -> > +required:\r -> > + - "#phy-cells"\r -> > + - compatible\r -> > + - reg\r -> > + - reg-names\r -> > + - clocks\r -> > + - clock-names\r -> > + - samsung,pmu-syscon\r -> \r -> Add:\r -> \r -> additionalProperties: false\r -> \r -> With that,\r -> \r -Will update the documentation as per your suggestion\r -\r -> Reviewed-by: Rob Herring <robh@kernel.org>\r ->\r -Thanks for review comments. After fixing, will add your review tag.\r - \r -> > +\r -> > +examples:\r -> > + - |\r -> > + #include <dt-bindings/clock/exynos7-clk.h>\r -> > +\r -> > + ufs_phy: ufs-phy@15571800 {\r -> > + compatible = "samsung,exynos7-ufs-phy";\r -> > + reg = <0x15571800 0x240>;\r -> > + reg-names = "phy-pma";\r -> > + samsung,pmu-syscon = <&pmu_system_controller>;\r -> > + #phy-cells = <0>;\r -> > + clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,\r -> > + <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,\r -> > + <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,\r -> > + <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;\r -> > + clock-names = "ref_clk", "rx1_symbol_clk",\r -> > + "rx0_symbol_clk", "tx0_symbol_clk";\r -> > +\r -> > + };\r -> > +...\r -> > --\r -> > 2.17.1\r +> > Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> +> > --- +> > .../bindings/phy/samsung,ufs-phy.yaml | 74 +++++++++++++++++++ +> > 1 file changed, 74 insertions(+) +> > create mode 100644 +> > Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > > +> > diff --git +> > a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +> > b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +> > new file mode 100644 +> > index 000000000000..352d5dda320d +> > --- /dev/null +> > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +> > @@ -0,0 +1,74 @@ +> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 +> > +--- +> > +$id: +> > +https://protect2.fireeye.com/url?k=5c35df0a-01ffeabd-5c345445-0cc47a3 +> > +003e8- +> aa6c980dab2ba33a&q=1&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2F +> > +phy%2Fsamsung%2Cufs-phy.yaml%23 +> > +$schema: +> > +https://protect2.fireeye.com/url?k=9734fc5e-cafec9e9-97357711-0cc47a3 +> > +003e8- +> 79d176b992774339&q=1&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schem +> > +as%2Fcore.yaml%23 +> > + +> > +title: Samsung SoC series UFS PHY Device Tree Bindings +> > + +> > +maintainers: +> > + - Alim Akhtar <alim.akhtar@samsung.com> +> > + +> > +properties: +> > + "#phy-cells": +> > + const: 0 +> > + +> > + compatible: +> > + enum: +> > + - samsung,exynos7-ufs-phy +> > + +> > + reg: +> > + maxItems: 1 +> > + description: PHY base register address +> +> Can drop the description. Doesn't add anything special. +> +> > + +> > + reg-names: +> > + items: +> > + - const: phy-pma +> > + +> > + clocks: +> > + items: +> > + - description: PLL reference clock +> > + - description: symbol clock for input symbol ( rx0-ch0 symbol clock) +> > + - description: symbol clock for input symbol ( rx1-ch1 symbol clock) +> > + - description: symbol clock for output symbol ( tx0 symbol +> > + clock) +> > + +> > + clock-names: +> > + items: +> > + - const: ref_clk +> > + - const: rx1_symbol_clk +> > + - const: rx0_symbol_clk +> > + - const: tx0_symbol_clk +> > + +> > + samsung,pmu-syscon: +> > + $ref: '/schemas/types.yaml#/definitions/phandle' +> > + description: phandle for PMU system controller interface, used to +> > + control pmu registers bits for ufs m-phy +> > + +> > +required: +> > + - "#phy-cells" +> > + - compatible +> > + - reg +> > + - reg-names +> > + - clocks +> > + - clock-names +> > + - samsung,pmu-syscon +> +> Add: +> +> additionalProperties: false +> +> With that, +> +Will update the documentation as per your suggestion + +> Reviewed-by: Rob Herring <robh@kernel.org> +> +Thanks for review comments. After fixing, will add your review tag. + +> > + +> > +examples: +> > + - | +> > + #include <dt-bindings/clock/exynos7-clk.h> +> > + +> > + ufs_phy: ufs-phy@15571800 { +> > + compatible = "samsung,exynos7-ufs-phy"; +> > + reg = <0x15571800 0x240>; +> > + reg-names = "phy-pma"; +> > + samsung,pmu-syscon = <&pmu_system_controller>; +> > + #phy-cells = <0>; +> > + clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, +> > + <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, +> > + <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, +> > + <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; +> > + clock-names = "ref_clk", "rx1_symbol_clk", +> > + "rx0_symbol_clk", "tx0_symbol_clk"; +> > + +> > + }; +> > +... +> > -- +> > 2.17.1 +> > + + + +_______________________________________________ +linux-arm-kernel mailing list +linux-arm-kernel@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N1/content_digest index e2ed9bb..898b966 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -6,17 +6,17 @@ "Subject\0RE: [PATCH v7 06/10] dt-bindings: phy: Document Samsung UFS PHY bindings\0" "Date\0Sat, 9 May 2020 06:06:10 +0530\0" "To\0'Rob Herring' <robh@kernel.org>\0" - "Cc\0<devicetree@vger.kernel.org>" - <linux-scsi@vger.kernel.org> - <krzk@kernel.org> - <avri.altman@wdc.com> - <martin.petersen@oracle.com> - <kwmad.kim@samsung.com> - <stanley.chu@mediatek.com> - <cang@codeaurora.org> - <linux-samsung-soc@vger.kernel.org> - <linux-arm-kernel@lists.infradead.org> - " <linux-kernel@vger.kernel.org>\0" + "Cc\0devicetree@vger.kernel.org" + linux-samsung-soc@vger.kernel.org + linux-scsi@vger.kernel.org + martin.petersen@oracle.com + linux-kernel@vger.kernel.org + krzk@kernel.org + kwmad.kim@samsung.com + avri.altman@wdc.com + cang@codeaurora.org + stanley.chu@mediatek.com + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Rob\n" @@ -37,121 +37,128 @@ "> > This patch documents Samsung UFS PHY device tree bindings\n" "> >\n" "> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>\n" - "> > Tested-by: Pawe\305\202 Chmiel <pawel.mikolaj.chmiel@gmail.com>\r\n" - "> > ---\r\n" - "> > .../bindings/phy/samsung,ufs-phy.yaml | 74 +++++++++++++++++++\r\n" - "> > 1 file changed, 74 insertions(+)\r\n" - "> > create mode 100644\r\n" - "> > Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\r\n" - "> >\r\n" - "> > diff --git\r\n" - "> > a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\r\n" - "> > b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\r\n" - "> > new file mode 100644\r\n" - "> > index 000000000000..352d5dda320d\r\n" - "> > --- /dev/null\r\n" - "> > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\r\n" - "> > @@ -0,0 +1,74 @@\r\n" - "> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2\r\n" - "> > +---\r\n" - "> > +$id:\r\n" - "> > +https://protect2.fireeye.com/url?k=5c35df0a-01ffeabd-5c345445-0cc47a3\r\n" - "> > +003e8-\r\n" - "> aa6c980dab2ba33a&q=1&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2F\r\n" - "> > +phy%2Fsamsung%2Cufs-phy.yaml%23\r\n" - "> > +$schema:\r\n" - "> > +https://protect2.fireeye.com/url?k=9734fc5e-cafec9e9-97357711-0cc47a3\r\n" - "> > +003e8-\r\n" - "> 79d176b992774339&q=1&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schem\r\n" - "> > +as%2Fcore.yaml%23\r\n" - "> > +\r\n" - "> > +title: Samsung SoC series UFS PHY Device Tree Bindings\r\n" - "> > +\r\n" - "> > +maintainers:\r\n" - "> > + - Alim Akhtar <alim.akhtar@samsung.com>\r\n" - "> > +\r\n" - "> > +properties:\r\n" - "> > + \"#phy-cells\":\r\n" - "> > + const: 0\r\n" - "> > +\r\n" - "> > + compatible:\r\n" - "> > + enum:\r\n" - "> > + - samsung,exynos7-ufs-phy\r\n" - "> > +\r\n" - "> > + reg:\r\n" - "> > + maxItems: 1\r\n" - "> > + description: PHY base register address\r\n" - "> \r\n" - "> Can drop the description. Doesn't add anything special.\r\n" - "> \r\n" - "> > +\r\n" - "> > + reg-names:\r\n" - "> > + items:\r\n" - "> > + - const: phy-pma\r\n" - "> > +\r\n" - "> > + clocks:\r\n" - "> > + items:\r\n" - "> > + - description: PLL reference clock\r\n" - "> > + - description: symbol clock for input symbol ( rx0-ch0 symbol clock)\r\n" - "> > + - description: symbol clock for input symbol ( rx1-ch1 symbol clock)\r\n" - "> > + - description: symbol clock for output symbol ( tx0 symbol\r\n" - "> > + clock)\r\n" - "> > +\r\n" - "> > + clock-names:\r\n" - "> > + items:\r\n" - "> > + - const: ref_clk\r\n" - "> > + - const: rx1_symbol_clk\r\n" - "> > + - const: rx0_symbol_clk\r\n" - "> > + - const: tx0_symbol_clk\r\n" - "> > +\r\n" - "> > + samsung,pmu-syscon:\r\n" - "> > + $ref: '/schemas/types.yaml#/definitions/phandle'\r\n" - "> > + description: phandle for PMU system controller interface, used to\r\n" - "> > + control pmu registers bits for ufs m-phy\r\n" - "> > +\r\n" - "> > +required:\r\n" - "> > + - \"#phy-cells\"\r\n" - "> > + - compatible\r\n" - "> > + - reg\r\n" - "> > + - reg-names\r\n" - "> > + - clocks\r\n" - "> > + - clock-names\r\n" - "> > + - samsung,pmu-syscon\r\n" - "> \r\n" - "> Add:\r\n" - "> \r\n" - "> additionalProperties: false\r\n" - "> \r\n" - "> With that,\r\n" - "> \r\n" - "Will update the documentation as per your suggestion\r\n" - "\r\n" - "> Reviewed-by: Rob Herring <robh@kernel.org>\r\n" - ">\r\n" - "Thanks for review comments. After fixing, will add your review tag.\r\n" - " \r\n" - "> > +\r\n" - "> > +examples:\r\n" - "> > + - |\r\n" - "> > + #include <dt-bindings/clock/exynos7-clk.h>\r\n" - "> > +\r\n" - "> > + ufs_phy: ufs-phy@15571800 {\r\n" - "> > + compatible = \"samsung,exynos7-ufs-phy\";\r\n" - "> > + reg = <0x15571800 0x240>;\r\n" - "> > + reg-names = \"phy-pma\";\r\n" - "> > + samsung,pmu-syscon = <&pmu_system_controller>;\r\n" - "> > + #phy-cells = <0>;\r\n" - "> > + clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,\r\n" - "> > + <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,\r\n" - "> > + <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,\r\n" - "> > + <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;\r\n" - "> > + clock-names = \"ref_clk\", \"rx1_symbol_clk\",\r\n" - "> > + \"rx0_symbol_clk\", \"tx0_symbol_clk\";\r\n" - "> > +\r\n" - "> > + };\r\n" - "> > +...\r\n" - "> > --\r\n" - "> > 2.17.1\r\n" - > > + "> > Tested-by: Pawe\305\202 Chmiel <pawel.mikolaj.chmiel@gmail.com>\n" + "> > ---\n" + "> > .../bindings/phy/samsung,ufs-phy.yaml | 74 +++++++++++++++++++\n" + "> > 1 file changed, 74 insertions(+)\n" + "> > create mode 100644\n" + "> > Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\n" + "> >\n" + "> > diff --git\n" + "> > a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\n" + "> > b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\n" + "> > new file mode 100644\n" + "> > index 000000000000..352d5dda320d\n" + "> > --- /dev/null\n" + "> > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml\n" + "> > @@ -0,0 +1,74 @@\n" + "> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2\n" + "> > +---\n" + "> > +$id:\n" + "> > +https://protect2.fireeye.com/url?k=5c35df0a-01ffeabd-5c345445-0cc47a3\n" + "> > +003e8-\n" + "> aa6c980dab2ba33a&q=1&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2F\n" + "> > +phy%2Fsamsung%2Cufs-phy.yaml%23\n" + "> > +$schema:\n" + "> > +https://protect2.fireeye.com/url?k=9734fc5e-cafec9e9-97357711-0cc47a3\n" + "> > +003e8-\n" + "> 79d176b992774339&q=1&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schem\n" + "> > +as%2Fcore.yaml%23\n" + "> > +\n" + "> > +title: Samsung SoC series UFS PHY Device Tree Bindings\n" + "> > +\n" + "> > +maintainers:\n" + "> > + - Alim Akhtar <alim.akhtar@samsung.com>\n" + "> > +\n" + "> > +properties:\n" + "> > + \"#phy-cells\":\n" + "> > + const: 0\n" + "> > +\n" + "> > + compatible:\n" + "> > + enum:\n" + "> > + - samsung,exynos7-ufs-phy\n" + "> > +\n" + "> > + reg:\n" + "> > + maxItems: 1\n" + "> > + description: PHY base register address\n" + "> \n" + "> Can drop the description. Doesn't add anything special.\n" + "> \n" + "> > +\n" + "> > + reg-names:\n" + "> > + items:\n" + "> > + - const: phy-pma\n" + "> > +\n" + "> > + clocks:\n" + "> > + items:\n" + "> > + - description: PLL reference clock\n" + "> > + - description: symbol clock for input symbol ( rx0-ch0 symbol clock)\n" + "> > + - description: symbol clock for input symbol ( rx1-ch1 symbol clock)\n" + "> > + - description: symbol clock for output symbol ( tx0 symbol\n" + "> > + clock)\n" + "> > +\n" + "> > + clock-names:\n" + "> > + items:\n" + "> > + - const: ref_clk\n" + "> > + - const: rx1_symbol_clk\n" + "> > + - const: rx0_symbol_clk\n" + "> > + - const: tx0_symbol_clk\n" + "> > +\n" + "> > + samsung,pmu-syscon:\n" + "> > + $ref: '/schemas/types.yaml#/definitions/phandle'\n" + "> > + description: phandle for PMU system controller interface, used to\n" + "> > + control pmu registers bits for ufs m-phy\n" + "> > +\n" + "> > +required:\n" + "> > + - \"#phy-cells\"\n" + "> > + - compatible\n" + "> > + - reg\n" + "> > + - reg-names\n" + "> > + - clocks\n" + "> > + - clock-names\n" + "> > + - samsung,pmu-syscon\n" + "> \n" + "> Add:\n" + "> \n" + "> additionalProperties: false\n" + "> \n" + "> With that,\n" + "> \n" + "Will update the documentation as per your suggestion\n" + "\n" + "> Reviewed-by: Rob Herring <robh@kernel.org>\n" + ">\n" + "Thanks for review comments. After fixing, will add your review tag.\n" + " \n" + "> > +\n" + "> > +examples:\n" + "> > + - |\n" + "> > + #include <dt-bindings/clock/exynos7-clk.h>\n" + "> > +\n" + "> > + ufs_phy: ufs-phy@15571800 {\n" + "> > + compatible = \"samsung,exynos7-ufs-phy\";\n" + "> > + reg = <0x15571800 0x240>;\n" + "> > + reg-names = \"phy-pma\";\n" + "> > + samsung,pmu-syscon = <&pmu_system_controller>;\n" + "> > + #phy-cells = <0>;\n" + "> > + clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,\n" + "> > + <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,\n" + "> > + <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,\n" + "> > + <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;\n" + "> > + clock-names = \"ref_clk\", \"rx1_symbol_clk\",\n" + "> > + \"rx0_symbol_clk\", \"tx0_symbol_clk\";\n" + "> > +\n" + "> > + };\n" + "> > +...\n" + "> > --\n" + "> > 2.17.1\n" + "> >\n" + "\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-arm-kernel mailing list\n" + "linux-arm-kernel@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -30c3ead9bc69ed2afba58f25688875d012ab7cf51ee33a6310796d94dab61fe6 +bb7811b3610524ea4bfe461e75d4eec4edb983b53b2e923abf3737d9ad191760
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