Does any body have HYNIX or AMIC 32M SDRAM reference cdoe?

[徐勝威 <rober@opnet.com.tw>]

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Hi All:

       I used HY57641620 * 2 total all 16M SDRAM at my MPC852T board, now i want to 
used HY57V281620ET-H * 2 or AMIC A43L3616-6 * 2 total all  32M SDRAM, but i don't know
how to setting UPM to control it, i need help.If you used another 32M SDRAM solution,
please tell me, thanks.


#define _NOT_USED_      0xFFFFFFFF

const uint sdram_table[] =   /* for HY57641620 * 2 16M  SDRAM */
{
        /* Single Read. (offset 0x0-0x4 in UPM RAM)     */
        /* Precharge and MRS(offset 0x5-0x7 in UPM RAM) */
        0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
        0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,

        /* Burst Read. (offset 0x8-0xf in UPM RAM) */
        0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
        0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

        /* Single Write. (offset 0x18-0x1F in UPM RAM) */
        0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

        /* Burst Write. (offset 20-2F in UPM RAM) */
        0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
        0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, _NOT_USED_,
        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

        /* Refresh timer expired (offset 30-3B in UPM RAM) */
        0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
        0xFFFFFC84, 0xFFFFFC07, 0xffffffff, _NOT_USED_,
        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

        /* Exception. (offset 3c-3f in UPM RAM) */
        0x7FFFFC07, _NOT_USED_, _NOT_USED_, _NOT_USED_
};

long int initdram(int board_type)
{
 volatile immap_t     *immap = (immap_t *)CFG_IMMR;
 volatile memctl8xx_t *memctl = &immap->im_memctl;

 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
  
 memctl->memc_mptpr = 0x0400;

 /*
  * Configure the refresh (mostly).  This needs to be
  * based upon processor clock speed and optimized to provide
  * the highest level of performance.  For multiple banks,
  * this time has to be divided by the number of banks.
  * Although it is not clear anywhere, it appears the
  * refresh steps through the chip selects for this UPM
  * on each refresh cycle.
  * We have to be careful changing
  * UPM registers after we ask it to run these commands.
  */

 memctl->memc_mamr = 0xD0904114;
 memctl->memc_mar = 0x00000088;
 udelay(200);

 memctl->memc_mcr = 0x80004105;     /* precharge */
 udelay(200);

 memctl->memc_mamr = 0xD0904114;
 memctl->memc_mcr = 0x80004830;     /* refresh */
 udelay(200);

 memctl->memc_mamr = 0xD0904114;
 memctl->memc_mcr = 0x80004106; 
 udelay(200);

 memctl->memc_or2 = 0xFE000A00;
 memctl->memc_br2 = 0x00000081;

 return (32 * 1024 *1024);
} /* end of initdram */

 

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