RE: [RFC] Relaxed PIO read vs. DMA write ordering

["Leonid Grossman" <leonid.grossman@s2io.com>]

> -----Original Message-----
> From: Christoph Hellwig [mailto:hch@infradead.org] 
> Sent: Thursday, January 08, 2004 9:54 AM
> To: Leonid Grossman
> Cc: 'Grant Grundler'; 'Jesse Barnes'; 
> linux-kernel@vger.kernel.org; jeremy@sgi.com; 'Matthew 
> Wilcox'; linux-pci@atrey.karlin.mff.cuni.cz; 
> Jame.Bottomley@steeleye.com
> Subject: Re: [RFC] Relaxed PIO read vs. DMA write ordering
> 
> 
> On Thu, Jan 08, 2004 at 08:23:49AM -0800, Leonid Grossman wrote:
> > Yes, this is exactly how (at least our 10GbE) PCI-X ASICs 
> work. If the 
> > RO bit is set, the device decides whether the transaction requires 
> > strong ordering, and sets RO attribute accordingly.
> 
> Do you have a pointer to the driver source?  This would 
> probably make a good reference driver for Jesse's suggestion.
> 

Right now the code goes to our OEMs and end-user customers along with
the cards; 
We are planning to submit the driver to 2.6 kernel in about 
3 weeks or so. 
At that point we will also 'unmask' it on s2io ftp site for downloads.

Leonid