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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c466838sm42932683f8f.49.2025.08.11.06.45.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 06:45:34 -0700 (PDT) Message-ID: <00bb0213-e4b3-457b-b5df-f575865b91ff@linaro.org> Date: Mon, 11 Aug 2025 15:45:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/1] target/arm: Trap PMCR when MDCR_EL2.TPMCR is set To: Smail AIDER , "qemu-devel@nongnu.org" Cc: Alexander Spyridakis , "zhangyue (BA)" , "Liuyutao(DRC)" , "mjt@tls.msk.ru" , Peter Maydell , "qemu-arm@nongnu.org" , "richard.henderson@linaro.org" References: <20250811112143.1577055-1-smail.aider@huawei.com> <20250811112143.1577055-2-smail.aider@huawei.com> <7402c0f3-326b-4a98-bd62-b8da998b4401@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 11/8/25 15:33, Smail AIDER wrote: > Hi Philippe, > > It is not just some refactoring. The last patch v3 is a squash of two previous patches v1 and v2. > Maybe I need to change the history description if not clear (I was talking from v3 point of view). > The purpose of the series is the main description itself. Please check the v1 below: > > https://patchew.org/QEMU/20250722131925.2119169-1-smail.aider@huawei.com/ Then please add a Cc tag (maintainer can do it if this v3 is OK, no need for v4): Cc: qemu-stable@nongnu.org > Other than that, the argument (is_pmcr) is correct. "isread" is not used in this case. Right, I missed it during review. Maybe we want to forward the arguments for clarity? -static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) +static CPAccessResult do_pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread, bool is_pmcr) Anyhow I'll let Richard review. No objection. > > -- > Best Regards, > Smail AIDER > E-Mail: smail.aider@huawei.com > Operating System Researcher/Developer > Dresden Research Center, OS Kernel Lab > Huawei Technologies Co., Ltd > > -----Original Message----- > From: Philippe Mathieu-Daudé > Sent: Monday, August 11, 2025 2:36 PM > To: Smail AIDER ; qemu-devel@nongnu.org > Cc: Alexander Spyridakis ; zhangyue (BA) ; Liuyutao(DRC) ; mjt@tls.msk.ru; Peter Maydell ; qemu-arm@nongnu.org; richard.henderson@linaro.org > Subject: Re: [PATCH v3 1/1] target/arm: Trap PMCR when MDCR_EL2.TPMCR is set > > Hi Smail, > > (no need to Cc qemu-stable with this patch, it is a simple refactor) > > On 11/8/25 13:21, Smail AIDER via wrote: >> From: Smail AIDER via >> >> Trap PMCR_EL0 or PMCR accesses to EL2 when MDCR_EL2.TPMCR is set. >> Similar to MDCR_EL2.TPM, MDCR_EL2.TPMCR allows trapping EL0 and EL1 >> accesses to the PMCR register to EL2. >> >> Signed-off-by: Smail AIDER >> Reviewed-by: Richard Henderson >> Message-Id: <20250722131925.2119169-1-smail.aider@huawei.com> >> --- >> target/arm/cpregs-pmu.c | 33 +++++++++++++++++++++++++-------- >> 1 file changed, 25 insertions(+), 8 deletions(-) >> >> diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c >> index 9c4431c18b..13392ddc4c 100644 >> --- a/target/arm/cpregs-pmu.c >> +++ b/target/arm/cpregs-pmu.c >> @@ -228,22 +228,27 @@ static bool event_supported(uint16_t number) >> return supported_event_map[number] != UNSUPPORTED_EVENT; >> } >> >> -static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, >> - bool isread) >> +static CPAccessResult do_pmreg_access(CPUARMState *env, bool is_pmcr) > > "bool is_pmcr" vs ... > >> +static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, >> + bool isread) > > ... "bool isread". > > I suppose we want to use "is_pmcr" here instead of "isread". > >> +{ >> + return do_pmreg_access(env, false); >> +} >> + >> +static CPAccessResult pmreg_access_pmcr(CPUARMState *env, const ARMCPRegInfo *ri, >> + bool isread) >> +{ >> + return do_pmreg_access(env, true); >> +} >> + >> static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, >> const ARMCPRegInfo *ri, >> bool isread) >> @@ -1187,14 +1204,14 @@ void define_pm_cpregs(ARMCPU *cpu) >> .fgt = FGT_PMCR_EL0, >> .type = ARM_CP_IO | ARM_CP_ALIAS, >> .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), >> - .accessfn = pmreg_access, >> + .accessfn = pmreg_access_pmcr, >> .readfn = pmcr_read, .raw_readfn = raw_read, >> .writefn = pmcr_write, .raw_writefn = raw_write, >> }; >> const ARMCPRegInfo pmcr64 = { >> .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, >> .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, >> - .access = PL0_RW, .accessfn = pmreg_access, >> + .access = PL0_RW, .accessfn = pmreg_access_pmcr, >> .fgt = FGT_PMCR_EL0, >> .type = ARM_CP_IO, >> .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), >