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Wed, 10 Jun 2020 05:33:49 -0700 (PDT) Received: from CBGR90WXYV0 ([54.239.6.186]) by smtp.gmail.com with ESMTPSA id m91sm3676447ede.96.2020.06.10.05.33.47 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Jun 2020 05:33:48 -0700 (PDT) From: Paul Durrant X-Google-Original-From: "Paul Durrant" To: "'Roger Pau Monne'" , References: <20200610115103.7592-1-roger.pau@citrix.com> <20200610115103.7592-2-roger.pau@citrix.com> In-Reply-To: <20200610115103.7592-2-roger.pau@citrix.com> Subject: RE: [PATCH for-4.14 1/2] x86/passthrough: do not assert edge triggered GSIs for PVH dom0 Date: Wed, 10 Jun 2020 13:33:46 +0100 Message-ID: <00e301d63f23$63c83a00$2b58ae00$@xen.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Content-Language: en-gb Thread-Index: AQJ/+0U2guq5J+wcejb54ge6+rzRyAJA9sgcp2xHeiA= X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Reply-To: paul@xen.org Cc: 'Andrew Cooper' , 'Wei Liu' , 'Jan Beulich' Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" > -----Original Message----- > From: Roger Pau Monne > Sent: 10 June 2020 12:51 > To: xen-devel@lists.xenproject.org > Cc: paul@xen.org; Roger Pau Monne ; Jan Beulich = ; Andrew > Cooper ; Wei Liu > Subject: [PATCH for-4.14 1/2] x86/passthrough: do not assert edge = triggered GSIs for PVH dom0 >=20 > Edge triggered interrupts do not assert the line, so the handling done > in Xen should also avoid asserting it. Asserting the line prevents > further edge triggered interrupts on the same vIO-APIC pin from being > delivered, since the line is not de-asserted. >=20 > One case of such kind of interrupt is the RTC timer, which is edge > triggered and available to a PVH dom0. Note this should not affect > domUs, as it only modifies the behavior of IDENTITY_GSI kind of passed > through interrupts. >=20 > Signed-off-by: Roger Pau Monn=C3=A9 > --- > xen/arch/x86/hvm/irq.c | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) >=20 > diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c > index 9c8adbc495..9a56543c1b 100644 > --- a/xen/arch/x86/hvm/irq.c > +++ b/xen/arch/x86/hvm/irq.c > @@ -169,9 +169,10 @@ void hvm_pci_intx_deassert( >=20 > void hvm_gsi_assert(struct domain *d, unsigned int gsi) > { > + int level =3D vioapic_get_trigger_mode(d, gsi); > struct hvm_irq *hvm_irq =3D hvm_domain_irq(d); >=20 > - if ( gsi >=3D hvm_irq->nr_gsis ) > + if ( gsi >=3D hvm_irq->nr_gsis || level < 0 ) > { > ASSERT_UNREACHABLE(); > return; > @@ -186,9 +187,10 @@ void hvm_gsi_assert(struct domain *d, unsigned = int gsi) > * to know if the GSI is pending or not. > */ > spin_lock(&d->arch.hvm.irq_lock); > - if ( !hvm_irq->gsi_assert_count[gsi] ) > + if ( !level || !hvm_irq->gsi_assert_count[gsi] ) We have definitions of VIOAPIC_EDGE_TRIG and VIOAPIC_LEVEL_TRIG. It = seems odd not to use them here. Paul > { > - hvm_irq->gsi_assert_count[gsi] =3D 1; > + if ( !level ) > + hvm_irq->gsi_assert_count[gsi] =3D 1; > assert_gsi(d, gsi); > } > spin_unlock(&d->arch.hvm.irq_lock); > @@ -196,11 +198,12 @@ void hvm_gsi_assert(struct domain *d, unsigned = int gsi) >=20 > void hvm_gsi_deassert(struct domain *d, unsigned int gsi) > { > + int level =3D vioapic_get_trigger_mode(d, gsi); > struct hvm_irq *hvm_irq =3D hvm_domain_irq(d); >=20 > - if ( gsi >=3D hvm_irq->nr_gsis ) > + if ( level <=3D 0 || gsi >=3D hvm_irq->nr_gsis ) > { > - ASSERT_UNREACHABLE(); > + ASSERT(level =3D=3D 0 && gsi < hvm_irq->nr_gsis); > return; > } >=20 > -- > 2.26.2