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Wed, 10 Jun 2020 07:49:19 -0700 (PDT) Received: from CBGR90WXYV0 ([54.239.6.186]) by smtp.gmail.com with ESMTPSA id d16sm7087862wmd.42.2020.06.10.07.49.17 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Jun 2020 07:49:18 -0700 (PDT) From: Paul Durrant X-Google-Original-From: "Paul Durrant" To: "'Roger Pau Monne'" , References: <20200610142923.9074-1-roger.pau@citrix.com> <20200610142923.9074-2-roger.pau@citrix.com> In-Reply-To: <20200610142923.9074-2-roger.pau@citrix.com> Subject: RE: [PATCH for-4.14 v2 1/2] x86/passthrough: do not assert edge triggered GSIs for PVH dom0 Date: Wed, 10 Jun 2020 15:49:17 +0100 Message-ID: <00e401d63f36$51cd4800$f567d800$@xen.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Content-Language: en-gb Thread-Index: AQHx2+DDRjLQssRal4XfU2f+2Pe7FQGgF1ZFqI2zmqA= X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Reply-To: paul@xen.org Cc: 'Andrew Cooper' , 'Wei Liu' , 'Jan Beulich' Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" > -----Original Message----- > From: Roger Pau Monne > Sent: 10 June 2020 15:29 > To: xen-devel@lists.xenproject.org > Cc: paul@xen.org; Roger Pau Monne ; Jan Beulich = ; Andrew > Cooper ; Wei Liu > Subject: [PATCH for-4.14 v2 1/2] x86/passthrough: do not assert edge = triggered GSIs for PVH dom0 >=20 > Edge triggered interrupts do not assert the line, so the handling done > in Xen should also avoid asserting it. Asserting the line prevents > further edge triggered interrupts on the same vIO-APIC pin from being > delivered, since the line is not de-asserted. >=20 > One case of such kind of interrupt is the RTC timer, which is edge > triggered and available to a PVH dom0. Note this should not affect > domUs, as it only modifies the behavior of IDENTITY_GSI kind of passed > through interrupts. >=20 > Signed-off-by: Roger Pau Monn=C3=A9 > Acked-by: Andrew Cooper Reviewed-by: Paul Durrant Release-acked-by: Paul Durrant > --- > Changes since v1: > - Compare the triggering against VIOAPIC_{EDGE/LEVEL}_TRIG. > --- > xen/arch/x86/hvm/irq.c | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) >=20 > diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c > index 9c8adbc495..fd02cf2e8d 100644 > --- a/xen/arch/x86/hvm/irq.c > +++ b/xen/arch/x86/hvm/irq.c > @@ -169,9 +169,10 @@ void hvm_pci_intx_deassert( >=20 > void hvm_gsi_assert(struct domain *d, unsigned int gsi) > { > + int trig =3D vioapic_get_trigger_mode(d, gsi); > struct hvm_irq *hvm_irq =3D hvm_domain_irq(d); >=20 > - if ( gsi >=3D hvm_irq->nr_gsis ) > + if ( gsi >=3D hvm_irq->nr_gsis || trig < 0 ) > { > ASSERT_UNREACHABLE(); > return; > @@ -186,9 +187,10 @@ void hvm_gsi_assert(struct domain *d, unsigned = int gsi) > * to know if the GSI is pending or not. > */ > spin_lock(&d->arch.hvm.irq_lock); > - if ( !hvm_irq->gsi_assert_count[gsi] ) > + if ( trig =3D=3D VIOAPIC_EDGE_TRIG || = !hvm_irq->gsi_assert_count[gsi] ) > { > - hvm_irq->gsi_assert_count[gsi] =3D 1; > + if ( trig =3D=3D VIOAPIC_LEVEL_TRIG ) > + hvm_irq->gsi_assert_count[gsi] =3D 1; > assert_gsi(d, gsi); > } > spin_unlock(&d->arch.hvm.irq_lock); > @@ -196,11 +198,12 @@ void hvm_gsi_assert(struct domain *d, unsigned = int gsi) >=20 > void hvm_gsi_deassert(struct domain *d, unsigned int gsi) > { > + int trig =3D vioapic_get_trigger_mode(d, gsi); > struct hvm_irq *hvm_irq =3D hvm_domain_irq(d); >=20 > - if ( gsi >=3D hvm_irq->nr_gsis ) > + if ( trig <=3D VIOAPIC_EDGE_TRIG || gsi >=3D hvm_irq->nr_gsis ) > { > - ASSERT_UNREACHABLE(); > + ASSERT(trig =3D=3D VIOAPIC_EDGE_TRIG && gsi < = hvm_irq->nr_gsis); > return; > } >=20 > -- > 2.26.2