From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56257) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqchA-0004k4-R1 for qemu-devel@nongnu.org; Mon, 26 Oct 2015 03:59:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zqch6-0001Xe-Pn for qemu-devel@nongnu.org; Mon, 26 Oct 2015 03:59:56 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:13787) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zqch6-0001X7-Jo for qemu-devel@nongnu.org; Mon, 26 Oct 2015 03:59:52 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NWT00KD0I7P7W60@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Mon, 26 Oct 2015 07:59:49 +0000 (GMT) From: Pavel Fedin References: <835124713dcd2ff8240460ae3df401ccb5f1f0ee.1445522263.git.p.fedin@samsung.com> In-reply-to: Date: Mon, 26 Oct 2015 10:59:48 +0300 Message-id: <00f801d10fc4$49a5bbe0$dcf133a0$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: quoted-printable Content-language: ru Subject: Re: [Qemu-devel] [RFC PATCH v3 3/4] hw/intc/arm_gicv3_kvm: Implement get/put functions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: 'Peter Maydell' Cc: 'Diana Craciun' , 'Shlomo Pongratz' , 'Shlomo Pongratz' , 'QEMU Developers' , 'Vijay Kilari' Hello! > > + reg =3D c->pendbaser & = (GICR_PENDBASER_OUTER_CACHEABILITY_MASK | > > + GICR_PENDBASER_ADDR_MASK | > > + GICR_PENDBASER_SHAREABILITY_MASK = | > > + = GICR_PENDBASER_CACHEABILITY_MASK); > > + if (!c->redist_ctlr & GICR_CTLR_ENABLE_LPIS) { > > + reg |=3D GICR_PENDBASER_PTZ; > > + } >=20 > Why does the state of the pendbaser register depend on state in the > redist_ctlr ? PTZ bit is write-only, we cannot read it back. And spec says that = setting PTZ is adviced while LPIs are not enabled, because it shortens = down the time of GIC initialization. So, i had to implement this small = heuristics here. Is this approach OK? > Worth a comment, whatever the answer is. I will. > > + kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®, false); > > + c->pendbaser =3D reg & = (GICR_PENDBASER_OUTER_CACHEABILITY_MASK | > > + GICR_PENDBASER_ADDR_MASK | > > + GICR_PENDBASER_SHAREABILITY_MASK = | > > + = GICR_PENDBASER_CACHEABILITY_MASK); >=20 > Why do we need to mask these values? I decided to do this at least for the case of KVM->TCG migration (as = far as i understand, such things are possible). In this case i think we = should not pollute our state with read-only bits, which get added by the = emulation code itself. > Do we not transfer ICC_SRE_EL1 because it's implemented as RO? > (I think that's right for no-irq/fiq-bypass, sysregs only.) Yes, also because looks like KVM is not going to implement GICv3 with = non-SRE mode, instead, if we want to run a legacy guest, we just = configure our host to provide GICv2 for it. I actually migrate only those CPU interface registers, which are saved = by the kernel code as part of guest's context. Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia