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Thu, 7 Aug 2025 06:56:38 +0000 (GMT) From: "Pankaj Dubey" To: "'Krzysztof Kozlowski'" , "'SeonGu Kang'" , "'Jesper Nilsson'" , "'Michael Turquette'" , "'Stephen Boyd'" , "'Rob Herring'" , "'Krzysztof Kozlowski'" , "'Conor Dooley'" , "'Sylwester Nawrocki'" , "'Chanwoo Choi'" , "'Alim Akhtar'" , "'Linus Walleij'" , "'Tomasz Figa'" , "'Catalin Marinas'" , "'Will Deacon'" , "'Arnd Bergmann'" Cc: "'kenkim'" , "'Jongshin Park'" , "'GunWoo Kim'" , "'HaGyeong Kim'" , "'GyoungBo Min'" , "'SungMin Park'" , "'Shradha Todi'" , "'Ravi Patel'" , "'Inbaraj E'" , "'Swathi K S'" , "'Hrishikesh'" , "'Dongjin Yang'" , "'Sang Min Kim'" , , , , , , , , In-Reply-To: Subject: RE: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC Date: Thu, 7 Aug 2025 12:26:27 +0530 Message-ID: <013301dc0768$6f58dc40$4e0a94c0$@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQGJY/8wx4BImu0YLFPVfwpfqUmFNgKXZrJuAgeQag4A83Fv2QHBXkcOAZGX7yoCWvFQXwHgUMUuAOJp+3+0i+6vkA== Content-Language: en-us X-CMS-MailID: 20250807065644epcas5p125fc65c6d04e995d92f2afd90b7b1ade X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250721064006epcas5p4617b0450e69f72c94d2b3ae7b1d200e7 References: <20250710002047.1573841-1-ksk4725@coasia.com> <847e908b-1073-46ea-93f3-1f36cc93d8b8@kernel.org> <99977f38-f055-46ed-8eb0-4b757da2bcdd@kernel.org> <000501dc06ab$37f09440$a7d1bcc0$@samsung.com> <002001dc06b1$540dc980$fc295c80$@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250806_235655_132941_8B8F686B X-CRM114-Status: GOOD ( 37.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > Subject: Re: =5BPATCH 00/16=5D Add support for the Axis ARTPEC-8 SoC >=20 > On 06/08/2025 11:05, Pankaj Dubey wrote: > > > >> Also SAME strict DT compliance profile will be applied. (see more on > >> that below) > >> > >>> > >>> Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we bel= ieve > it's > >> reasonable > >>> to create a separate directory for it, similar to FSD. > >> > >> No. It was a mistake for FSD to keep it separate why? Because there is > >> no single non-Samsung stuff there. I am afraid exactly the same will > >> happen there. > >> > > > > I am not sure, why you are saying this as a mistake, in case next versi= on of > FSD >=20 >=20 > My mistake that I agreed on that, based on promise that =22there will be > non Samsung stuff=22 and that =22non Samsung stuff=22 never happened. >=20 I am not authorized to comment on FSD's non Samsung stuff at this moment. But I got your point. > > or ARTPEC is manufactured (ODM) by another vendor in that case, won't i= t > > create problems? >=20 >=20 > No problems here. Non-Samsung Artpec/Axis soc will not go there. It will > go the top-level axis directory, just like artpec-6 >=20 Okay, understood. I assume Axis team will be fine with this approach. Let me align with them internally and address all the review comments in v2= .=20 >=20 > > > > For example ARTPEC-6/7 (ARM based) have their own directories as > =22arch/arm/boot/dts/axis/=22 > > These were not Samsung (ODM) manufactures SoCs. > > > > But ARTPEC-8/9 (ARM64) based SoCs are samsung manufactured. What if > the next version say > > ARTPEC-10 is not samsung manufactured, so different version of products > (SoCs) from > > same vendor (OEM), in this case Axis, will have code in separate direct= ories > and with different maintainers? >=20 > It will be the same with Google Pixel for whatever they decide in the > future. dts/exynos/google/ + dts/google/. >=20 > I know that this is not ideal, but for me grouping samsung stuff > together is far more important, because there is much, much more to > share between two SoCs designed by Samsung, than Axis-9 and future > non-Samsung Axis-10. And I have =60git grep=60 as argument: > git grep compatible -- arch/arm64/boot/dts/tesla/ >=20 > and point me to any Tesla IP. Zero results. >=20 >=20 > > > >> Based on above list of blocks this should be done like Google is done, > >> so it goes as subdirectory of samsung (exynos). Can be called axis or > >> artpec-8. > > > > I will suggest to keep axis, knowing the fact that sooner after artpec-= 8 > patches gets approved and merged > > we have plan to upstream artpec-9 (ARM64, Samsung manufactured) as > well. > > > >> > >> To clarify: Only this SoC, not others which are not Samsung. > >> > >>> > >>> We will remove Samsung and Coasia teams from the maintainers list in > v2 > >> and only > >>> Axis team will be maintainer. > >> > >> A bit unexpected or rather: just use names of people who WILL be > >> maintaining it. If this is Jesper and Lars, great. Just don't add > >> entries just because they are managers. > > > > AFAIK, Jesper will be taking care. > > > >> > >>> > >>> Maintainer list for previous generation of Axis chips (ARM based) is > already > >> present, > >>> so this will be merged into that. > >> > >> Existing Artpec entry does not have tree mentioned, so if you choose > >> above, you must not add the tree, since the tree is provided by Samsun= g > SoC. > >> > > > > OK > > > >> OTOH, how are you going to add there strict DT compliance? Existing ax= is > >> is not following this, but artpec-8, as a Samsung derivative, MUST > >> FOLLOW strict DT compliance. And this should be clearly marked in > >> maintainer entry, just like everywhere else. > >> > > > > As I said this is tricky situation, though artpec-8 is derivative of sa= msung, we > can't confirm > > if future versions (> 9) will be samsung derivative. > > > > But this would be case for all such custom ASIC manufactured by samsung= , > so I would like to > > understand how this will be handled? >=20 >=20 > I suggest to do the same as Google and when I say Google in this email, > I mean Pixel/GS101. Google was easier because there was no prior entry > and Axis has, so you will have two Axis entries. But I don't see how we > can add clean-dts profiles to the existing Axis entry, if you decide to > include Artpec-8 in that one. >=20 Okay we will have separate dts profile aligned with Exynos DT compliance fo= r ARM64 based Axis SoCs which are manufactured by Samsung at this moment.=20 >=20 > Best regards, > Krzysztof