From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [PATCH] drm/i915: set persistent mode for fbc
Date: Sun, 03 Jul 2011 12:01:47 +0100
Message-ID: <013811$m5eno@fmsmga002.fm.intel.com>
References: <1309549723-13144-1-git-send-email-ben@bwidawsk.net>
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To: Ben Widawsky <ben@bwidawsk.net>, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

I think we can make the patch and resulting code a bit more
comprehensible...

On Fri,  1 Jul 2011 12:48:43 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> This seems to fix my bugs with sna enabled.
> 
> We should collect some power numbers, and validate it works on ILK
> before upstreaming. (And read more about what it actually does).
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 804ac4d..4b94d71 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1607,6 +1607,8 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>  		I915_WRITE(SNB_DPFC_CTL_SA,
>  			   SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
>  		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
> +		/* Set persistent mode */
> +		I915_WRITE(ILK_DPFC_CONTROL, 1 << 25);
/* Set persistent mode for front-buffer rendering and to detect direct
 * writes through the CPU */
I915_WRITE(ILK_DPFC_CONTROL,
           I915_READ(ILK_DPFC_CONTROL) | DPFC_CTL_PERSISTENT_MODE);
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre