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From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Kandpal, Suraj" <suraj.kandpal@intel.com>,
	"Murthy, Arun R" <arun.r.murthy@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Cc: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: RE: [PATCH] drm/i915/scaler: Prune YUV420 modes against the max source width
Date: Thu, 08 Oct 2026 17:07:59 +0300	[thread overview]
Message-ID: <013890ff0c99723aeb304a0a6997543ba646524d@intel.com> (raw)
In-Reply-To: <DS4PPFE901A304F1782FA1CD962D6DDE3BFE3942@DS4PPFE901A304F.namprd11.prod.outlook.com>

On Wed, 07 Oct 2026, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> Subject: [PATCH] drm/i915/scaler: Prune YUV420 modes against the max
>> source width
>> 
>> skl_scaler_mode_valid() compares the mode's hdisplay against the pipe scaler
>> maximum source height instead of the maximum source width, so single pipe
>> YUV420 modes are pruned against the wrong limit.
>> 
>> Commit 3347b55f2c6c ("drm/i915/xe3lpd: Prune modes for YUV420")
>> intended to reject modes whose hdisplay exceeds the scaler horizontal source
>
> I think no need to mention  this commit since you already mention this in fixes
> Also 
> Cc: stable@vger.kernel.org

Yeah we have 'dim fixes' for this.

$ dim fixes 3347b55f2c6c
Fixes: 3347b55f2c6c ("drm/i915/xe3lpd: Prune modes for YUV420")
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> #v2
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Cc: <stable@vger.kernel.org> # v6.18+

Don't put all of it in the trailers, but it gives you an idea who should
perhaps be Cc'd and what the stable target should be.


BR,
Jani.


>
> Otherwise LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
>> limit, since pipe scaling does not support YUV420 for a source width above
>> 4096. Comparing against max_h makes the check far too permissive from
>> display 12 onwards, where max_h is 8192, and too strict on display 11, where
>> max_h is 4096 while the horizontal limit is 5120.
>> 
>> Compare against max_w instead.
>> 
>> Fixes: 3347b55f2c6c ("drm/i915/xe3lpd: Prune modes for YUV420")
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
>> b/drivers/gpu/drm/i915/display/skl_scaler.c
>> index 7994b983d509..7e65c4fffbc0 100644
>> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
>> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
>> @@ -145,7 +145,7 @@ skl_scaler_mode_valid(struct intel_display *display,
>> 
>>  	if (num_joined_pipes < 2 && output_format ==
>> INTEL_OUTPUT_FORMAT_YCBCR420) {
>>  		skl_scaler_max_src_size(display, &max_w, &max_h);
>> -		if (mode->hdisplay > max_h)
>> +		if (mode->hdisplay > max_w)
>>  			return MODE_NO_420;
>>  	}
>> 
>> --
>> 2.25.1
>

-- 
Jani Nikula, Intel

  reply	other threads:[~2026-10-08 14:08 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-07  7:06 [PATCH] drm/i915/scaler: Prune YUV420 modes against the max source width Arun R Murthy
2026-10-07  7:16 ` ✓ CI.KUnit: success for " Patchwork
2026-10-07  7:17 ` [PATCH] " sashiko-bot
2026-10-07  7:58 ` ✓ i915.CI.BAT: success for " Patchwork
2026-10-07  8:03 ` [PATCH] " Kandpal, Suraj
2026-10-08 14:07   ` Jani Nikula [this message]
2026-10-07  8:24 ` ✓ Xe.CI.BAT: success for " Patchwork
2026-10-07  9:17 ` ✓ Xe.CI.FULL: " Patchwork
2026-10-07 10:42 ` ✓ i915.CI.Full: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2026-10-08  4:18 [PATCH] " Arun R Murthy
2026-10-08  4:30 ` sashiko-bot

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