diff for duplicates of <013c01d3c052$ca49ecd0$5eddc670$@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index fb6baa3..aa6d063 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,24 +3,29 @@ > -----Original Message----- > From: Stephen Boyd <sboyd@kernel.org> > Sent: Monday, March 19, 2018 18:50 -> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel@lists.infradead.org; +> To: Ilia Lin <ilialin@codeaurora.org>; = +linux-arm-kernel@lists.infradead.org; > linux-arm-msm@vger.kernel.org; linux-clk@vger.kernel.org; > sboyd@codeaurora.org > Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; > rnayak@codeaurora.org; robh@kernel.org; will.deacon@arm.com; -> amit.kucheria@linaro.org; tfinkel@codeaurora.org; ilialin@codeaurora.org; +> amit.kucheria@linaro.org; tfinkel@codeaurora.org; = +ilialin@codeaurora.org; > nicolas.dechesne@linaro.org; celster@codeaurora.org -> Subject: Re: [PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on probe -> +> Subject: Re: [PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on = +probe +>=20 > Quoting Ilia Lin (2018-02-14 05:59:49) -> > The PLLs must be prepared enabled during the probe to be accessible by +> > The PLLs must be prepared enabled during the probe to be accessible = +by > > the OPPs. Otherwise an OPP may switch to non-enabled clock. -> +>=20 > Sounds like an OPP problem. -And again, it could be solved by a platform specific cpufreq driver. Worth it? +And again, it could be solved by a platform specific cpufreq driver. = +Worth it? -> +>=20 > > > > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > > --- @@ -37,17 +42,18 @@ And again, it could be solved by a platform specific cpufreq driver. Worth it? > > #include <linux/regmap.h> > > - > > +#include <linux/clk-provider.h> -> +>=20 > Please leave a newline between linux/* and local includes. Will be changed in the next spin. -> +>=20 > > #include "clk-alpha-pll.h" > > > > #define VCO(a, b, c) { \ > > @@ -376,6 +376,18 @@ struct clk_hw_clks { -> > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); +> > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, = +&altpll_config); > > clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, > > &altpll_config); > > @@ -56,25 +62,28 @@ Will be changed in the next spin. > > + clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk); > > + clk_prepare_enable(pwrcl_pll.clkr.hw.clk); > > + clk_prepare_enable(perfcl_pll.clkr.hw.clk); -> +>=20 > And this can't be done by the cpufreq-dt driver? Are you suggesting changing the cpufreq-dt as well? -> +>=20 > > + > > + /* Set initial boot frequencies for power/perf PLLs */ > > + clk_set_rate(pwrcl_alt_pll.clkr.hw.clk, 652800000); > > + clk_set_rate(perfcl_alt_pll.clkr.hw.clk, 652800000); > > + clk_set_rate(pwrcl_pll.clkr.hw.clk, 652800000); > > + clk_set_rate(perfcl_pll.clkr.hw.clk, 652800000); -> +>=20 > We have assigned rates in DT for this. -I assumed that the clock driver can live without the OPP table and any cpufreq driver. Or do you mean adding this as parameters for the kryocc DT node? +I assumed that the clock driver can live without the OPP table and any = +cpufreq driver. Or do you mean adding this as parameters for the kryocc = +DT node? -> +>=20 > > + -> > ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); +> > ret =3D clk_notifier_register(pwrcl_pmux.clkr.hw.clk, = +&pwrcl_pmux.nb); > > if (ret) > > return ret; diff --git a/a/content_digest b/N1/content_digest index 666abe9..990b10e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,19 +5,19 @@ "Subject\0RE: [PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on probe\0" "Date\0Tue, 20 Mar 2018 15:53:08 +0200\0" "To\0'Stephen Boyd' <sboyd@kernel.org>" - linux-arm-kernel@lists.infradead.org - linux-arm-msm@vger.kernel.org - linux-clk@vger.kernel.org - " sboyd@codeaurora.org\0" - "Cc\0mark.rutland@arm.com" - devicetree@vger.kernel.org - rnayak@codeaurora.org - robh@kernel.org - will.deacon@arm.com - amit.kucheria@linaro.org - tfinkel@codeaurora.org - nicolas.dechesne@linaro.org - " celster@codeaurora.org\0" + <linux-arm-kernel@lists.infradead.org> + <linux-arm-msm@vger.kernel.org> + <linux-clk@vger.kernel.org> + " <sboyd@codeaurora.org>\0" + "Cc\0<mark.rutland@arm.com>" + <devicetree@vger.kernel.org> + <rnayak@codeaurora.org> + <robh@kernel.org> + <will.deacon@arm.com> + <amit.kucheria@linaro.org> + <tfinkel@codeaurora.org> + <nicolas.dechesne@linaro.org> + " <celster@codeaurora.org>\0" "\00:1\0" "b\0" "\n" @@ -25,24 +25,29 @@ "> -----Original Message-----\n" "> From: Stephen Boyd <sboyd@kernel.org>\n" "> Sent: Monday, March 19, 2018 18:50\n" - "> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel@lists.infradead.org;\n" + "> To: Ilia Lin <ilialin@codeaurora.org>; =\n" + "linux-arm-kernel@lists.infradead.org;\n" "> linux-arm-msm@vger.kernel.org; linux-clk@vger.kernel.org;\n" "> sboyd@codeaurora.org\n" "> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org;\n" "> rnayak@codeaurora.org; robh@kernel.org; will.deacon@arm.com;\n" - "> amit.kucheria@linaro.org; tfinkel@codeaurora.org; ilialin@codeaurora.org;\n" + "> amit.kucheria@linaro.org; tfinkel@codeaurora.org; =\n" + "ilialin@codeaurora.org;\n" "> nicolas.dechesne@linaro.org; celster@codeaurora.org\n" - "> Subject: Re: [PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on probe\n" - "> \n" + "> Subject: Re: [PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on =\n" + "probe\n" + ">=20\n" "> Quoting Ilia Lin (2018-02-14 05:59:49)\n" - "> > The PLLs must be prepared enabled during the probe to be accessible by\n" + "> > The PLLs must be prepared enabled during the probe to be accessible =\n" + "by\n" "> > the OPPs. Otherwise an OPP may switch to non-enabled clock.\n" - "> \n" + ">=20\n" "> Sounds like an OPP problem.\n" "\n" - "And again, it could be solved by a platform specific cpufreq driver. Worth it?\n" + "And again, it could be solved by a platform specific cpufreq driver. =\n" + "Worth it?\n" "\n" - "> \n" + ">=20\n" "> >\n" "> > Signed-off-by: Ilia Lin <ilialin@codeaurora.org>\n" "> > ---\n" @@ -59,17 +64,18 @@ "> > #include <linux/regmap.h>\n" "> > -\n" "> > +#include <linux/clk-provider.h>\n" - "> \n" + ">=20\n" "> Please leave a newline between linux/* and local includes.\n" "\n" "Will be changed in the next spin.\n" "\n" - "> \n" + ">=20\n" "> > #include \"clk-alpha-pll.h\"\n" "> >\n" "> > #define VCO(a, b, c) { \\\n" "> > @@ -376,6 +376,18 @@ struct clk_hw_clks {\n" - "> > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);\n" + "> > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, =\n" + "&altpll_config);\n" "> > clk_alpha_pll_configure(&pwrcl_alt_pll, regmap,\n" "> > &altpll_config);\n" "> >\n" @@ -78,27 +84,30 @@ "> > + clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);\n" "> > + clk_prepare_enable(pwrcl_pll.clkr.hw.clk);\n" "> > + clk_prepare_enable(perfcl_pll.clkr.hw.clk);\n" - "> \n" + ">=20\n" "> And this can't be done by the cpufreq-dt driver?\n" "\n" "Are you suggesting changing the cpufreq-dt as well?\n" "\n" - "> \n" + ">=20\n" "> > +\n" "> > + /* Set initial boot frequencies for power/perf PLLs */\n" "> > + clk_set_rate(pwrcl_alt_pll.clkr.hw.clk, 652800000);\n" "> > + clk_set_rate(perfcl_alt_pll.clkr.hw.clk, 652800000);\n" "> > + clk_set_rate(pwrcl_pll.clkr.hw.clk, 652800000);\n" "> > + clk_set_rate(perfcl_pll.clkr.hw.clk, 652800000);\n" - "> \n" + ">=20\n" "> We have assigned rates in DT for this.\n" "\n" - "I assumed that the clock driver can live without the OPP table and any cpufreq driver. Or do you mean adding this as parameters for the kryocc DT node?\n" + "I assumed that the clock driver can live without the OPP table and any =\n" + "cpufreq driver. Or do you mean adding this as parameters for the kryocc =\n" + "DT node?\n" "\n" - "> \n" + ">=20\n" "> > +\n" - "> > ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);\n" + "> > ret =3D clk_notifier_register(pwrcl_pmux.clkr.hw.clk, =\n" + "&pwrcl_pmux.nb);\n" "> > if (ret)\n" > > return ret; -120ed7ef68427273d5d9037f6b82ad3469c5de7234c79a895bfbaf2b78ff5cd3 +eb7b65d806ebe6b9bd8b9a06a9f1b5e186f4cbde95a9d331b856f2414a2d9037
diff --git a/a/1.txt b/N2/1.txt index fb6baa3..e65946f 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -3,13 +3,13 @@ > -----Original Message----- > From: Stephen Boyd <sboyd@kernel.org> > Sent: Monday, March 19, 2018 18:50 -> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel@lists.infradead.org; -> linux-arm-msm@vger.kernel.org; linux-clk@vger.kernel.org; -> sboyd@codeaurora.org -> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; -> rnayak@codeaurora.org; robh@kernel.org; will.deacon@arm.com; -> amit.kucheria@linaro.org; tfinkel@codeaurora.org; ilialin@codeaurora.org; -> nicolas.dechesne@linaro.org; celster@codeaurora.org +> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel at lists.infradead.org; +> linux-arm-msm at vger.kernel.org; linux-clk at vger.kernel.org; +> sboyd at codeaurora.org +> Cc: mark.rutland at arm.com; devicetree at vger.kernel.org; +> rnayak at codeaurora.org; robh at kernel.org; will.deacon at arm.com; +> amit.kucheria at linaro.org; tfinkel at codeaurora.org; ilialin at codeaurora.org; +> nicolas.dechesne at linaro.org; celster at codeaurora.org > Subject: Re: [PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on probe > > Quoting Ilia Lin (2018-02-14 05:59:49) diff --git a/a/content_digest b/N2/content_digest index 666abe9..9d3cc12 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,23 +1,10 @@ "ref\01518616792-29028-1-git-send-email-ilialin@codeaurora.org\0" "ref\01518616792-29028-8-git-send-email-ilialin@codeaurora.org\0" "ref\0152147821849.242365.7709382599118820578@swboyd.mtv.corp.google.com\0" - "From\0<ilialin@codeaurora.org>\0" - "Subject\0RE: [PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on probe\0" + "From\0ilialin@codeaurora.org (ilialin at codeaurora.org)\0" + "Subject\0[PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on probe\0" "Date\0Tue, 20 Mar 2018 15:53:08 +0200\0" - "To\0'Stephen Boyd' <sboyd@kernel.org>" - linux-arm-kernel@lists.infradead.org - linux-arm-msm@vger.kernel.org - linux-clk@vger.kernel.org - " sboyd@codeaurora.org\0" - "Cc\0mark.rutland@arm.com" - devicetree@vger.kernel.org - rnayak@codeaurora.org - robh@kernel.org - will.deacon@arm.com - amit.kucheria@linaro.org - tfinkel@codeaurora.org - nicolas.dechesne@linaro.org - " celster@codeaurora.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" @@ -25,13 +12,13 @@ "> -----Original Message-----\n" "> From: Stephen Boyd <sboyd@kernel.org>\n" "> Sent: Monday, March 19, 2018 18:50\n" - "> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel@lists.infradead.org;\n" - "> linux-arm-msm@vger.kernel.org; linux-clk@vger.kernel.org;\n" - "> sboyd@codeaurora.org\n" - "> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org;\n" - "> rnayak@codeaurora.org; robh@kernel.org; will.deacon@arm.com;\n" - "> amit.kucheria@linaro.org; tfinkel@codeaurora.org; ilialin@codeaurora.org;\n" - "> nicolas.dechesne@linaro.org; celster@codeaurora.org\n" + "> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel at lists.infradead.org;\n" + "> linux-arm-msm at vger.kernel.org; linux-clk at vger.kernel.org;\n" + "> sboyd at codeaurora.org\n" + "> Cc: mark.rutland at arm.com; devicetree at vger.kernel.org;\n" + "> rnayak at codeaurora.org; robh at kernel.org; will.deacon at arm.com;\n" + "> amit.kucheria at linaro.org; tfinkel at codeaurora.org; ilialin at codeaurora.org;\n" + "> nicolas.dechesne at linaro.org; celster at codeaurora.org\n" "> Subject: Re: [PATCH v3 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on probe\n" "> \n" "> Quoting Ilia Lin (2018-02-14 05:59:49)\n" @@ -101,4 +88,4 @@ "> > if (ret)\n" > > return ret; -120ed7ef68427273d5d9037f6b82ad3469c5de7234c79a895bfbaf2b78ff5cd3 +99ba0749a7dff86ad42d90f60a2a89e72c68577eb8d6a5416148791105ed20c5
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.