From: Vijay Balakrishna <vijayb@linux.microsoft.com>
To: Borislav Petkov <bp@alien8.de>, Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
James Morse <james.morse@arm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Robert Richter <rric@kernel.org>,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
Tyler Hicks <code@tyhicks.com>, Marc Zyngier <maz@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
devicetree@vger.kernel.org
Subject: Re: [v8 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72
Date: Wed, 7 May 2025 21:14:30 -0700 [thread overview]
Message-ID: <013cab30-7314-46bb-afd6-156632835fcc@linux.microsoft.com> (raw)
In-Reply-To: <20250505091044.GCaBiAlCFqVgV7-3TJ@fat_crate.local>
On 5/5/25 02:10, Borislav Petkov wrote:
> On Sun, May 04, 2025 at 05:27:38PM -0700, Vijay Balakrishna wrote:
>> Hello,
>>
>> This is an attempt to revive [v5] series. I have attempted to address comments
>> and suggestions from Marc Zyngier since [v5]. Additionally, I have extended
>
> I'd like to hear from ARM folks here, whether this makes sense to have still.
>
>> support for A72 processors. Testing the driver on a problematic A72 SoC
>> has led to the detection of Correctable Errors (CEs). Below are logs captured
>> from the problematic SoC during various boot instances.
>>
>> [ 876.896022] EDAC DEVICE0: CE: cortex-arm64-edac instance: cpu2 block: L1 count: 1 'L1-D Data RAM correctable error(s) on CPU 2'
>>
>> [ 3700.978086] EDAC DEVICE0: CE: cortex-arm64-edac instance: cpu2 block: L1 count: 1 'L1-D Data RAM correctable error(s) on CPU 2'
>>
>> [ 976.956158] EDAC DEVICE0: CE: cortex-arm64-edac instance: cpu2 block: L1 count: 1 'L1-D Data RAM correctable error(s) on CPU 2'
>>
>> [ 1427.933606] EDAC DEVICE0: CE: cortex-arm64-edac instance: cpu2 block: L1 count: 1 'L1-D Data RAM correctable error(s) on CPU 2'
>>
>> [ 192.959911] EDAC DEVICE0: CE: cortex-arm64-edac instance: cpu2 block: L1 count: 1 'L1-D Data RAM correctable error(s) on CPU 2'
>>
>> Our primary focus is on A72. We have a significant number of A72-based systems
>
> Then zap the support for the other CPUs as supporting those is futile.
>
> cortex_arm64_l1_l2.c - I don't want an EDAC driver per RAS functional unit.
> Call this edac_a72 or whatever, which will contain all A72 RAS functionality
> support. ARM folks will give you a good idea here if you don't have.
>
> Also, I'd need at least a reviewer entry to MAINTAINERS for patches to this
> driver because you'll be the only ones testing this as you have vested
> interest in this working.
>
> The dt patch needs a reviewed-by too.
>
> Once that is addressed, I'll take a look.
>
> Thx.
>
Thank you, Boris.
I will soon be posting a new series featuring only A72 functionality.
Could the ARM folks on Cc please comment on additional changes we can
include for A72?
Tyler and I can serve as joint reviewers, and I'll update the
MAINTAINERS file accordingly.
Krzysztof, I would appreciate your reviewed-by for the DT patch when I
post the next version.
Thanks,
Vijay
prev parent reply other threads:[~2025-05-08 4:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-05 0:27 [v8 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72 Vijay Balakrishna
2025-05-05 0:27 ` [PATCH 1/2] drivers/edac: " Vijay Balakrishna
2025-05-05 0:27 ` [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Vijay Balakrishna
2025-05-12 19:30 ` Rob Herring
2025-05-05 9:10 ` [v8 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72 Borislav Petkov
2025-05-08 4:14 ` Vijay Balakrishna [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=013cab30-7314-46bb-afd6-156632835fcc@linux.microsoft.com \
--to=vijayb@linux.microsoft.com \
--cc=bp@alien8.de \
--cc=code@tyhicks.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=james.morse@arm.com \
--cc=krzk+dt@kernel.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=maz@kernel.org \
--cc=mchehab@kernel.org \
--cc=robh@kernel.org \
--cc=rric@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=tony.luck@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.