diff for duplicates of <017101d3c07b$9367cc40$ba3764c0$@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 4e6cb9f..60bb8b2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,29 +3,32 @@ Will be fixed and respinned. > -----Original Message----- > From: Stephen Boyd <sboyd@kernel.org> > Sent: Monday, March 19, 2018 19:48 -> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel@lists.infradead.org; +> To: Ilia Lin <ilialin@codeaurora.org>; = +linux-arm-kernel@lists.infradead.org; > linux-arm-msm@vger.kernel.org; linux-clk@vger.kernel.org; > sboyd@codeaurora.org > Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; > rnayak@codeaurora.org; robh@kernel.org; will.deacon@arm.com; -> amit.kucheria@linaro.org; tfinkel@codeaurora.org; ilialin@codeaurora.org; +> amit.kucheria@linaro.org; tfinkel@codeaurora.org; = +ilialin@codeaurora.org; > nicolas.dechesne@linaro.org; celster@codeaurora.org -> Subject: Re: [PATCH v3 05/10] clk: qcom: cpu-8996: Add support to switch to +> Subject: Re: [PATCH v3 05/10] clk: qcom: cpu-8996: Add support to = +switch to > alternate PLL -> +>=20 > Quoting Ilia Lin (2018-02-14 05:59:47) > > From: Rajendra Nayak <rnayak@codeaurora.org> > > > > Each of the CPU clusters on msm8996 and powered via a primary -> +>=20 > s/and/are/ -> +>=20 > > PLL and a secondary PLL. The primary PLL is what drivers the -> +>=20 > s/drivers/drives/ -> +>=20 > I make the same typo all the time! -> +>=20 > > CPU clk, except for times when we are reprogramming the PLL itself, > > when we temporarily switch to an alternate PLL. > > Use clock rate change notifiers to support this. @@ -61,60 +64,69 @@ Will be fixed and respinned. > > return 0; > > } > > -> > +int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, +> > +int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long = +event, > > + void *data) > > +{ > > + int ret; -> > + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); +> > + struct clk_cpu_8996_mux *cpuclk =3D = +to_clk_cpu_8996_mux_nb(nb); > > + > > + switch (event) { > > + case PRE_RATE_CHANGE: -> > + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, +> > + ret =3D = +clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, > ALT_INDEX); > > + break; > > + case POST_RATE_CHANGE: -> > + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, +> > + ret =3D = +clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, > PLL_INDEX); > > + break; > > + default: -> > + ret = 0; +> > + ret =3D 0; > > + break; > > + } > > + > > + return notifier_from_errno(ret); }; > > + -> > const struct clk_ops clk_cpu_8996_mux_ops = { -> > .set_parent = clk_cpu_8996_mux_set_parent, -> > .get_parent = clk_cpu_8996_mux_get_parent, @@ -237,6 +262,7 @@ +> > const struct clk_ops clk_cpu_8996_mux_ops =3D { +> > .set_parent =3D clk_cpu_8996_mux_set_parent, +> > .get_parent =3D clk_cpu_8996_mux_get_parent, @@ -237,6 = ++262,7 @@ > > static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) -> > .shift = 0, -> > .width = 2, -> > .pll = &pwrcl_pll.clkr.hw, -> > + .nb.notifier_call = cpu_clk_notifier_cb, -> > .clkr.hw.init = &(struct clk_init_data) { -> > .name = "pwrcl_pmux", -> > .parent_names = (const char *[]){ @@ -256,6 +282,7 @@ +> > .shift =3D 0, +> > .width =3D 2, +> > .pll =3D &pwrcl_pll.clkr.hw, +> > + .nb.notifier_call =3D cpu_clk_notifier_cb, +> > .clkr.hw.init =3D &(struct clk_init_data) { +> > .name =3D "pwrcl_pmux", +> > .parent_names =3D (const char *[]){ @@ -256,6 +282,7 = +@@ > > static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) -> > .shift = 0, -> > .width = 2, -> > .pll = &perfcl_pll.clkr.hw, -> > + .nb.notifier_call = cpu_clk_notifier_cb, -> > .clkr.hw.init = &(struct clk_init_data) { -> > .name = "perfcl_pmux", -> > .parent_names = (const char *[]){ @@ -331,6 +358,14 @@ +> > .shift =3D 0, +> > .width =3D 2, +> > .pll =3D &perfcl_pll.clkr.hw, +> > + .nb.notifier_call =3D cpu_clk_notifier_cb, +> > .clkr.hw.init =3D &(struct clk_init_data) { +> > .name =3D "perfcl_pmux", +> > .parent_names =3D (const char *[]){ @@ -331,6 = ++358,14 @@ > > struct clk_hw_clks { -> > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); +> > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, = +&altpll_config); > > clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, > > &altpll_config); > > -> > + ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); +> > + ret =3D clk_notifier_register(pwrcl_pmux.clkr.hw.clk, = +&pwrcl_pmux.nb); > > + if (ret) > > + return ret; > > + -> > + ret = clk_notifier_register(perfcl_pmux.clkr.hw.clk, +> > + ret =3D clk_notifier_register(perfcl_pmux.clkr.hw.clk, > &perfcl_pmux.nb); > > + if (ret) > > + return ret; > > + -> +>=20 > Please resend this with the other patches that need rework. diff --git a/a/content_digest b/N1/content_digest index 7f08229..d7b6327 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,19 +5,19 @@ "Subject\0RE: [PATCH v3 05/10] clk: qcom: cpu-8996: Add support to switch to alternate PLL\0" "Date\0Tue, 20 Mar 2018 20:45:04 +0200\0" "To\0'Stephen Boyd' <sboyd@kernel.org>" - linux-arm-kernel@lists.infradead.org - linux-arm-msm@vger.kernel.org - linux-clk@vger.kernel.org - " sboyd@codeaurora.org\0" - "Cc\0mark.rutland@arm.com" - devicetree@vger.kernel.org - rnayak@codeaurora.org - robh@kernel.org - will.deacon@arm.com - amit.kucheria@linaro.org - tfinkel@codeaurora.org - nicolas.dechesne@linaro.org - " celster@codeaurora.org\0" + <linux-arm-kernel@lists.infradead.org> + <linux-arm-msm@vger.kernel.org> + <linux-clk@vger.kernel.org> + " <sboyd@codeaurora.org>\0" + "Cc\0<mark.rutland@arm.com>" + <devicetree@vger.kernel.org> + <rnayak@codeaurora.org> + <robh@kernel.org> + <will.deacon@arm.com> + <amit.kucheria@linaro.org> + <tfinkel@codeaurora.org> + <nicolas.dechesne@linaro.org> + " <celster@codeaurora.org>\0" "\00:1\0" "b\0" "Will be fixed and respinned.\n" @@ -25,29 +25,32 @@ "> -----Original Message-----\n" "> From: Stephen Boyd <sboyd@kernel.org>\n" "> Sent: Monday, March 19, 2018 19:48\n" - "> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel@lists.infradead.org;\n" + "> To: Ilia Lin <ilialin@codeaurora.org>; =\n" + "linux-arm-kernel@lists.infradead.org;\n" "> linux-arm-msm@vger.kernel.org; linux-clk@vger.kernel.org;\n" "> sboyd@codeaurora.org\n" "> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org;\n" "> rnayak@codeaurora.org; robh@kernel.org; will.deacon@arm.com;\n" - "> amit.kucheria@linaro.org; tfinkel@codeaurora.org; ilialin@codeaurora.org;\n" + "> amit.kucheria@linaro.org; tfinkel@codeaurora.org; =\n" + "ilialin@codeaurora.org;\n" "> nicolas.dechesne@linaro.org; celster@codeaurora.org\n" - "> Subject: Re: [PATCH v3 05/10] clk: qcom: cpu-8996: Add support to switch to\n" + "> Subject: Re: [PATCH v3 05/10] clk: qcom: cpu-8996: Add support to =\n" + "switch to\n" "> alternate PLL\n" - "> \n" + ">=20\n" "> Quoting Ilia Lin (2018-02-14 05:59:47)\n" "> > From: Rajendra Nayak <rnayak@codeaurora.org>\n" "> >\n" "> > Each of the CPU clusters on msm8996 and powered via a primary\n" - "> \n" + ">=20\n" "> s/and/are/\n" - "> \n" + ">=20\n" "> > PLL and a secondary PLL. The primary PLL is what drivers the\n" - "> \n" + ">=20\n" "> s/drivers/drives/\n" - "> \n" + ">=20\n" "> I make the same typo all the time!\n" - "> \n" + ">=20\n" "> > CPU clk, except for times when we are reprogramming the PLL itself,\n" "> > when we temporarily switch to an alternate PLL.\n" "> > Use clock rate change notifiers to support this.\n" @@ -83,62 +86,71 @@ "> > return 0;\n" "> > }\n" "> >\n" - "> > +int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,\n" + "> > +int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long =\n" + "event,\n" "> > + void *data)\n" "> > +{\n" "> > + int ret;\n" - "> > + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);\n" + "> > + struct clk_cpu_8996_mux *cpuclk =3D =\n" + "to_clk_cpu_8996_mux_nb(nb);\n" "> > +\n" "> > + switch (event) {\n" "> > + case PRE_RATE_CHANGE:\n" - "> > + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,\n" + "> > + ret =3D =\n" + "clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,\n" "> ALT_INDEX);\n" "> > + break;\n" "> > + case POST_RATE_CHANGE:\n" - "> > + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,\n" + "> > + ret =3D =\n" + "clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,\n" "> PLL_INDEX);\n" "> > + break;\n" "> > + default:\n" - "> > + ret = 0;\n" + "> > + ret =3D 0;\n" "> > + break;\n" "> > + }\n" "> > +\n" "> > + return notifier_from_errno(ret); };\n" "> > +\n" - "> > const struct clk_ops clk_cpu_8996_mux_ops = {\n" - "> > .set_parent = clk_cpu_8996_mux_set_parent,\n" - "> > .get_parent = clk_cpu_8996_mux_get_parent, @@ -237,6 +262,7 @@\n" + "> > const struct clk_ops clk_cpu_8996_mux_ops =3D {\n" + "> > .set_parent =3D clk_cpu_8996_mux_set_parent,\n" + "> > .get_parent =3D clk_cpu_8996_mux_get_parent, @@ -237,6 =\n" + "+262,7 @@\n" "> > static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)\n" - "> > .shift = 0,\n" - "> > .width = 2,\n" - "> > .pll = &pwrcl_pll.clkr.hw,\n" - "> > + .nb.notifier_call = cpu_clk_notifier_cb,\n" - "> > .clkr.hw.init = &(struct clk_init_data) {\n" - "> > .name = \"pwrcl_pmux\",\n" - "> > .parent_names = (const char *[]){ @@ -256,6 +282,7 @@\n" + "> > .shift =3D 0,\n" + "> > .width =3D 2,\n" + "> > .pll =3D &pwrcl_pll.clkr.hw,\n" + "> > + .nb.notifier_call =3D cpu_clk_notifier_cb,\n" + "> > .clkr.hw.init =3D &(struct clk_init_data) {\n" + "> > .name =3D \"pwrcl_pmux\",\n" + "> > .parent_names =3D (const char *[]){ @@ -256,6 +282,7 =\n" + "@@\n" "> > static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)\n" - "> > .shift = 0,\n" - "> > .width = 2,\n" - "> > .pll = &perfcl_pll.clkr.hw,\n" - "> > + .nb.notifier_call = cpu_clk_notifier_cb,\n" - "> > .clkr.hw.init = &(struct clk_init_data) {\n" - "> > .name = \"perfcl_pmux\",\n" - "> > .parent_names = (const char *[]){ @@ -331,6 +358,14 @@\n" + "> > .shift =3D 0,\n" + "> > .width =3D 2,\n" + "> > .pll =3D &perfcl_pll.clkr.hw,\n" + "> > + .nb.notifier_call =3D cpu_clk_notifier_cb,\n" + "> > .clkr.hw.init =3D &(struct clk_init_data) {\n" + "> > .name =3D \"perfcl_pmux\",\n" + "> > .parent_names =3D (const char *[]){ @@ -331,6 =\n" + "+358,14 @@\n" "> > struct clk_hw_clks {\n" - "> > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);\n" + "> > clk_alpha_pll_configure(&perfcl_alt_pll, regmap, =\n" + "&altpll_config);\n" "> > clk_alpha_pll_configure(&pwrcl_alt_pll, regmap,\n" "> > &altpll_config);\n" "> >\n" - "> > + ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);\n" + "> > + ret =3D clk_notifier_register(pwrcl_pmux.clkr.hw.clk, =\n" + "&pwrcl_pmux.nb);\n" "> > + if (ret)\n" "> > + return ret;\n" "> > +\n" - "> > + ret = clk_notifier_register(perfcl_pmux.clkr.hw.clk,\n" + "> > + ret =3D clk_notifier_register(perfcl_pmux.clkr.hw.clk,\n" "> &perfcl_pmux.nb);\n" "> > + if (ret)\n" "> > + return ret;\n" "> > +\n" - "> \n" + ">=20\n" > Please resend this with the other patches that need rework. -98ab962216f88ad304d6ab5d35a14b8080ed5447e3a79147abcedd995bc2bbc2 +6278c2904b63159e72747f6f44396c55a1e6db3fd849753e05c50a20b3d21989
diff --git a/a/1.txt b/N2/1.txt index 4e6cb9f..bbc2f82 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -3,13 +3,13 @@ Will be fixed and respinned. > -----Original Message----- > From: Stephen Boyd <sboyd@kernel.org> > Sent: Monday, March 19, 2018 19:48 -> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel@lists.infradead.org; -> linux-arm-msm@vger.kernel.org; linux-clk@vger.kernel.org; -> sboyd@codeaurora.org -> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; -> rnayak@codeaurora.org; robh@kernel.org; will.deacon@arm.com; -> amit.kucheria@linaro.org; tfinkel@codeaurora.org; ilialin@codeaurora.org; -> nicolas.dechesne@linaro.org; celster@codeaurora.org +> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel at lists.infradead.org; +> linux-arm-msm at vger.kernel.org; linux-clk at vger.kernel.org; +> sboyd at codeaurora.org +> Cc: mark.rutland at arm.com; devicetree at vger.kernel.org; +> rnayak at codeaurora.org; robh at kernel.org; will.deacon at arm.com; +> amit.kucheria at linaro.org; tfinkel at codeaurora.org; ilialin at codeaurora.org; +> nicolas.dechesne at linaro.org; celster at codeaurora.org > Subject: Re: [PATCH v3 05/10] clk: qcom: cpu-8996: Add support to switch to > alternate PLL > diff --git a/a/content_digest b/N2/content_digest index 7f08229..c689169 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,23 +1,10 @@ "ref\01518616792-29028-1-git-send-email-ilialin@codeaurora.org\0" "ref\01518616792-29028-6-git-send-email-ilialin@codeaurora.org\0" "ref\0152148167517.242365.13429407450120461901@swboyd.mtv.corp.google.com\0" - "From\0<ilialin@codeaurora.org>\0" - "Subject\0RE: [PATCH v3 05/10] clk: qcom: cpu-8996: Add support to switch to alternate PLL\0" + "From\0ilialin@codeaurora.org (ilialin at codeaurora.org)\0" + "Subject\0[PATCH v3 05/10] clk: qcom: cpu-8996: Add support to switch to alternate PLL\0" "Date\0Tue, 20 Mar 2018 20:45:04 +0200\0" - "To\0'Stephen Boyd' <sboyd@kernel.org>" - linux-arm-kernel@lists.infradead.org - linux-arm-msm@vger.kernel.org - linux-clk@vger.kernel.org - " sboyd@codeaurora.org\0" - "Cc\0mark.rutland@arm.com" - devicetree@vger.kernel.org - rnayak@codeaurora.org - robh@kernel.org - will.deacon@arm.com - amit.kucheria@linaro.org - tfinkel@codeaurora.org - nicolas.dechesne@linaro.org - " celster@codeaurora.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Will be fixed and respinned.\n" @@ -25,13 +12,13 @@ "> -----Original Message-----\n" "> From: Stephen Boyd <sboyd@kernel.org>\n" "> Sent: Monday, March 19, 2018 19:48\n" - "> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel@lists.infradead.org;\n" - "> linux-arm-msm@vger.kernel.org; linux-clk@vger.kernel.org;\n" - "> sboyd@codeaurora.org\n" - "> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org;\n" - "> rnayak@codeaurora.org; robh@kernel.org; will.deacon@arm.com;\n" - "> amit.kucheria@linaro.org; tfinkel@codeaurora.org; ilialin@codeaurora.org;\n" - "> nicolas.dechesne@linaro.org; celster@codeaurora.org\n" + "> To: Ilia Lin <ilialin@codeaurora.org>; linux-arm-kernel at lists.infradead.org;\n" + "> linux-arm-msm at vger.kernel.org; linux-clk at vger.kernel.org;\n" + "> sboyd at codeaurora.org\n" + "> Cc: mark.rutland at arm.com; devicetree at vger.kernel.org;\n" + "> rnayak at codeaurora.org; robh at kernel.org; will.deacon at arm.com;\n" + "> amit.kucheria at linaro.org; tfinkel at codeaurora.org; ilialin at codeaurora.org;\n" + "> nicolas.dechesne at linaro.org; celster at codeaurora.org\n" "> Subject: Re: [PATCH v3 05/10] clk: qcom: cpu-8996: Add support to switch to\n" "> alternate PLL\n" "> \n" @@ -141,4 +128,4 @@ "> \n" > Please resend this with the other patches that need rework. -98ab962216f88ad304d6ab5d35a14b8080ed5447e3a79147abcedd995bc2bbc2 +423a16080f5d0df02ad96ee67c90c553671f8feae3543ff7b426a921fafabf34
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