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Mon, 17 Mar 2025 12:33:11 -0700 (PDT) Received: from DESKTOPUU50BPD ([2603:6000:a500:306:3131:60d1:4874:e2c7]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-476bb611c83sm57423131cf.2.2025.03.17.12.33.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Mar 2025 12:33:10 -0700 (PDT) From: To: "'Brian Cain'" , Cc: , , , , , , , , , "'Brian Cain'" References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> <20250301052845.1012069-12-brian.cain@oss.qualcomm.com> In-Reply-To: <20250301052845.1012069-12-brian.cain@oss.qualcomm.com> Subject: RE: [PATCH 11/39] target/hexagon: Add representation to count cycles Date: Mon, 17 Mar 2025 14:33:09 -0500 Message-ID: <017e01db9773$6ac9e0d0$405da270$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIWUu77rEigiK0ljjjo9ZdCZqs5mQG2Ccj6svSOcwA= Content-Language: en-us X-Antivirus: Norton (VPS 250317-4, 3/17/2025), Outbound message X-Antivirus-Status: Clean Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=ltaylorsimpson@gmail.com; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > -----Original Message----- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org; > philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng; > quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com; > alex.bennee@linaro.org; quic_mburton@quicinc.com; > sidneym@quicinc.com; Brian Cain > Subject: [PATCH 11/39] target/hexagon: Add representation to count cycles > > From: Brian Cain > > The PCYCLE register can be enabled to indicate accumulated clock cycles. > > Signed-off-by: Brian Cain > --- > target/hexagon/cpu.h | 3 ++- > target/hexagon/cpu.c | 3 +++ > target/hexagon/machine.c | 25 ++++++++++++++++++++++++- > 3 files changed, 29 insertions(+), 2 deletions(-) > > diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index > 1549c4f1f0..4b9c9873dc 100644 > --- a/target/hexagon/cpu.h > +++ b/target/hexagon/cpu.h > @@ -113,7 +113,8 @@ typedef struct CPUArchState { > target_ulong stack_start; > > uint8_t slot_cancelled; > - > + uint64_t t_cycle_count; > + uint64_t *g_pcycle_base; > #ifndef CONFIG_USER_ONLY > /* Some system registers are per thread and some are global. */ > target_ulong t_sreg[NUM_SREGS]; > diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index > 84a96a194b..89a051b41d 100644 > --- a/target/hexagon/cpu.c > +++ b/target/hexagon/cpu.c > @@ -335,6 +335,7 @@ static void hexagon_cpu_reset_hold(Object *obj, > ResetType type) > > if (cs->cpu_index == 0) { > arch_set_system_reg(env, HEX_SREG_MODECTL, 0x1); > + *(env->g_pcycle_base) = 0; See discussion on shared resources. > } > mmu_reset(env); > arch_set_system_reg(env, HEX_SREG_HTID, cs->cpu_index); @@ -396,10 > +397,12 @@ static void hexagon_cpu_realize(DeviceState *dev, Error > **errp) #ifndef CONFIG_USER_ONLY > if (cs->cpu_index == 0) { > env->g_sreg = g_new0(target_ulong, NUM_SREGS); > + env->g_pcycle_base = g_malloc0(sizeof(*env->g_pcycle_base)); Shared resource ... > } else { > CPUState *cpu0 = qemu_get_cpu(0); > CPUHexagonState *env0 = cpu_env(cpu0); > env->g_sreg = env0->g_sreg; > + env->g_pcycle_base = env0->g_pcycle_base; Shared resource ...