From: E Shattow <e@freeshell.de>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Hal Feng <hal.feng@starfivetech.com>
Cc: u-boot@lists.denx.de, Leo <ycliang@andestech.com>,
Tom Rini <trini@konsulko.com>, Rick Chen <rick@andestech.com>,
Sumit Garg <sumit.garg@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Subject: Re: [RFC 01/10] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts
Date: Tue, 2 Sep 2025 09:17:41 -0700 [thread overview]
Message-ID: <01a5ff2b-bc20-4670-93ce-2b66df408b96@freeshell.de> (raw)
In-Reply-To: <f8ed3792-70ca-498f-9ce7-65040860db07@canonical.com>
Hello Hal, and Heinrich,
On 8/29/25 00:19, Heinrich Schuchardt wrote:
> On 29.08.25 08:09, Hal Feng wrote:
>> Some node in this file are not used by the upcoming VisionFive 2 Lite
>> board. Move them to the board dts to prepare for adding the new
>> VisionFive 2 Lite device tree.
>>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
> LGTM
>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
>
NAK
Better to drop jh7110-common-u-boot.dtsi from U-Boot [1]. Also we can
drop jh7110-u-boot.dtsi file but that does require some additional work:
- upstream dt-binding memory-controllers/starfive,jh7110-dmc.yaml [2]
- upstream devicetree changes adding memory controller [3]
- upstream bootph-pre-ram hints [4]
- implement cpufreq driver
- refactor drivers/ram/starfive/starfive_ddr.c to use common clock
framework and delete 'clock-frequency = <2133>' in dts
I am not interested in writing U-Boot drivers. Hal, can you make the
needed improvements in U-Boot for cpufreq and memory controller drivers?
1: https://lore.kernel.org/u-boot/20250815050315.62956-1-e@freeshell.de/
2: https://lore.kernel.org/lkml/20250823100159.203925-2-e@freeshell.de/
3: https://lore.kernel.org/lkml/20250823100159.203925-3-e@freeshell.de/
4: https://lore.kernel.org/lkml/20250823100159.203925-4-e@freeshell.de/
Thanks, -E Shattow
>> ---
>> .../src/riscv/starfive/jh7110-common.dtsi | 22 ---------
>> .../jh7110-deepcomputing-fml13v01.dts | 49 +++++++++++++++++++
>> .../src/riscv/starfive/jh7110-milkv-mars.dts | 49 +++++++++++++++++++
>> .../riscv/starfive/jh7110-pine64-star64.dts | 49 +++++++++++++++++++
>> .../jh7110-starfive-visionfive-2.dtsi | 46 +++++++++++++++++
>> dts/upstream/src/riscv/starfive/jh7110.dtsi | 16 ------
>> 6 files changed, 193 insertions(+), 38 deletions(-)
>>
>> diff --git a/dts/upstream/src/riscv/starfive/jh7110-common.dtsi b/dts/
>> upstream/src/riscv/starfive/jh7110-common.dtsi
>> index 4baeb981d4d..9d3d03ad2ed 100644
>> --- a/dts/upstream/src/riscv/starfive/jh7110-common.dtsi
>> +++ b/dts/upstream/src/riscv/starfive/jh7110-common.dtsi
>> @@ -272,15 +272,9 @@
>> assigned-clock-rates = <50000000>;
>> bus-width = <8>;
>> bootph-pre-ram;
>> - cap-mmc-highspeed;
>> - mmc-ddr-1_8v;
>> - mmc-hs200-1_8v;
>> - cap-mmc-hw-reset;
>> post-power-on-delay-ms = <200>;
>> pinctrl-names = "default";
>> pinctrl-0 = <&mmc0_pins>;
>> - vmmc-supply = <&vcc_3v3>;
>> - vqmmc-supply = <&emmc_vdd>;
>> status = "okay";
>> };
>> @@ -290,12 +284,7 @@
>> assigned-clock-rates = <50000000>;
>> bus-width = <4>;
>> bootph-pre-ram;
>> - no-sdio;
>> - no-mmc;
>> - cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
>> - disable-wp;
>> cap-sd-highspeed;
>> - post-power-on-delay-ms = <200>;
>> pinctrl-names = "default";
>> pinctrl-0 = <&mmc1_pins>;
>> status = "okay";
>> @@ -439,17 +428,6 @@
>> };
>> mmc0_pins: mmc0-0 {
>> - rst-pins {
>> - pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
>> - GPOEN_ENABLE,
>> - GPI_NONE)>;
>> - bias-pull-up;
>> - drive-strength = <12>;
>> - input-disable;
>> - input-schmitt-disable;
>> - slew-rate = <0>;
>> - };
>> -
>> mmc-pins {
>> pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
>> <PINMUX(PAD_SD0_CMD, 0)>,
>> diff --git a/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-
>> fml13v01.dts b/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-
>> fml13v01.dts
>> index f2857d021d6..5a2a41a7e8c 100644
>> --- a/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts
>> +++ b/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts
>> @@ -11,6 +11,55 @@
>> compatible = "deepcomputing,fml13v01", "starfive,jh7110";
>> };
>> +&cpu_opp {
>> + opp-375000000 {
>> + opp-hz = /bits/ 64 <375000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-750000000 {
>> + opp-hz = /bits/ 64 <750000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-1500000000 {
>> + opp-hz = /bits/ 64 <1500000000>;
>> + opp-microvolt = <1040000>;
>> + };
>> +};
>> +
>> +&mmc0 {
>> + cap-mmc-highspeed;
>> + cap-mmc-hw-reset;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + vmmc-supply = <&vcc_3v3>;
>> + vqmmc-supply = <&emmc_vdd>;
>> +};
>> +
>> +&mmc0_pins {
>> + rst-pins {
>> + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
>> + GPOEN_ENABLE,
>> + GPI_NONE)>;
>> + bias-pull-up;
>> + drive-strength = <12>;
>> + input-disable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> +};
>> +
>> +&mmc1 {
>> + no-sdio;
>> + no-mmc;
>> + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
>> + disable-wp;
>> + post-power-on-delay-ms = <200>;
>> +};
>> +
>> &pcie1 {
>> perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
>> phys = <&pciephy1>;
>> diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts b/
>> dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
>> index 3bd62ab7852..0c90facc4ee 100644
>> --- a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
>> +++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
>> @@ -11,6 +11,25 @@
>> compatible = "milkv,mars", "starfive,jh7110";
>> };
>> +&cpu_opp {
>> + opp-375000000 {
>> + opp-hz = /bits/ 64 <375000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-750000000 {
>> + opp-hz = /bits/ 64 <750000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-1500000000 {
>> + opp-hz = /bits/ 64 <1500000000>;
>> + opp-microvolt = <1040000>;
>> + };
>> +};
>> +
>> &gmac0 {
>> starfive,tx-use-rgmii-clk;
>> assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
>> @@ -22,6 +41,36 @@
>> status = "okay";
>> };
>> +&mmc0 {
>> + cap-mmc-highspeed;
>> + cap-mmc-hw-reset;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + vmmc-supply = <&vcc_3v3>;
>> + vqmmc-supply = <&emmc_vdd>;
>> +};
>> +
>> +&mmc0_pins {
>> + rst-pins {
>> + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
>> + GPOEN_ENABLE,
>> + GPI_NONE)>;
>> + bias-pull-up;
>> + drive-strength = <12>;
>> + input-disable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> +};
>> +
>> +&mmc1 {
>> + no-sdio;
>> + no-mmc;
>> + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
>> + disable-wp;
>> + post-power-on-delay-ms = <200>;
>> +};
>> +
>> &pcie0 {
>> status = "okay";
>> };
>> diff --git a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
>> b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
>> index 31e825be206..c9677aef9ff 100644
>> --- a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
>> +++ b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
>> @@ -14,6 +14,25 @@
>> };
>> };
>> +&cpu_opp {
>> + opp-375000000 {
>> + opp-hz = /bits/ 64 <375000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-750000000 {
>> + opp-hz = /bits/ 64 <750000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-1500000000 {
>> + opp-hz = /bits/ 64 <1500000000>;
>> + opp-microvolt = <1040000>;
>> + };
>> +};
>> +
>> &gmac0 {
>> starfive,tx-use-rgmii-clk;
>> assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
>> @@ -44,6 +63,36 @@
>> status = "okay";
>> };
>> +&mmc0 {
>> + cap-mmc-highspeed;
>> + cap-mmc-hw-reset;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + vmmc-supply = <&vcc_3v3>;
>> + vqmmc-supply = <&emmc_vdd>;
>> +};
>> +
>> +&mmc0_pins {
>> + rst-pins {
>> + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
>> + GPOEN_ENABLE,
>> + GPI_NONE)>;
>> + bias-pull-up;
>> + drive-strength = <12>;
>> + input-disable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> +};
>> +
>> +&mmc1 {
>> + no-sdio;
>> + no-mmc;
>> + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
>> + disable-wp;
>> + post-power-on-delay-ms = <200>;
>> +};
>> +
>> &pcie1 {
>> status = "okay";
>> };
>> diff --git a/dts/upstream/src/riscv/starfive/jh7110-starfive-
>> visionfive-2.dtsi b/dts/upstream/src/riscv/starfive/jh7110-starfive-
>> visionfive-2.dtsi
>> index 5f14afb2c24..d1e4206f125 100644
>> --- a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -13,6 +13,25 @@
>> };
>> };
>> +&cpu_opp {
>> + opp-375000000 {
>> + opp-hz = /bits/ 64 <375000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-750000000 {
>> + opp-hz = /bits/ 64 <750000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp-1500000000 {
>> + opp-hz = /bits/ 64 <1500000000>;
>> + opp-microvolt = <1040000>;
>> + };
>> +};
>> +
>> &gmac0 {
>> status = "okay";
>> };
>> @@ -38,9 +57,36 @@
>> };
>> &mmc0 {
>> + cap-mmc-highspeed;
>> + cap-mmc-hw-reset;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + vmmc-supply = <&vcc_3v3>;
>> + vqmmc-supply = <&emmc_vdd>;
>> non-removable;
>> };
>> +&mmc0_pins {
>> + rst-pins {
>> + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
>> + GPOEN_ENABLE,
>> + GPI_NONE)>;
>> + bias-pull-up;
>> + drive-strength = <12>;
>> + input-disable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> +};
>> +
>> +&mmc1 {
>> + no-sdio;
>> + no-mmc;
>> + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
>> + disable-wp;
>> + post-power-on-delay-ms = <200>;
>> +};
>> +
>> &pcie0 {
>> status = "okay";
>> };
>> diff --git a/dts/upstream/src/riscv/starfive/jh7110.dtsi b/dts/
>> upstream/src/riscv/starfive/jh7110.dtsi
>> index 0ba74ef0467..d2463399b95 100644
>> --- a/dts/upstream/src/riscv/starfive/jh7110.dtsi
>> +++ b/dts/upstream/src/riscv/starfive/jh7110.dtsi
>> @@ -200,22 +200,6 @@
>> cpu_opp: opp-table-0 {
>> compatible = "operating-points-v2";
>> opp-shared;
>> - opp-375000000 {
>> - opp-hz = /bits/ 64 <375000000>;
>> - opp-microvolt = <800000>;
>> - };
>> - opp-500000000 {
>> - opp-hz = /bits/ 64 <500000000>;
>> - opp-microvolt = <800000>;
>> - };
>> - opp-750000000 {
>> - opp-hz = /bits/ 64 <750000000>;
>> - opp-microvolt = <800000>;
>> - };
>> - opp-1500000000 {
>> - opp-hz = /bits/ 64 <1500000000>;
>> - opp-microvolt = <1040000>;
>> - };
>> };
>> thermal-zones {
>
next prev parent reply other threads:[~2025-09-02 16:17 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-29 6:09 [RFC 00/10] Add support for StarFive VisionFive 2 Lite board Hal Feng
2025-08-29 6:09 ` [RFC 01/10] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts Hal Feng
2025-08-29 7:19 ` Heinrich Schuchardt
2025-09-02 16:17 ` E Shattow [this message]
2025-10-22 9:59 ` Hal Feng
2025-10-22 11:26 ` E Shattow
2025-08-29 6:09 ` [RFC 02/10] riscv: dts: starfive: Add VisionFive 2 Lite board device tree Hal Feng
2025-09-02 20:03 ` E Shattow
2025-09-03 11:07 ` Sumit Garg
2025-09-03 12:03 ` Heinrich Schuchardt
2025-09-04 2:39 ` Hal Feng
2025-08-29 6:09 ` [RFC 03/10] eeprom: starfive: Simplify get_ddr_size_from_eeprom() Hal Feng
2025-08-29 7:33 ` Heinrich Schuchardt
2025-09-02 21:28 ` E Shattow
2025-09-02 22:18 ` Heinrich Schuchardt
2025-10-21 9:20 ` Hal Feng
2025-10-21 19:04 ` E Shattow
2025-08-29 6:09 ` [RFC 04/10] eeprom: starfive: Correct get_pcb_revision_from_eeprom() Hal Feng
2025-08-29 7:44 ` Heinrich Schuchardt
2025-09-02 7:44 ` Hal Feng
2025-09-02 22:12 ` E Shattow
2025-09-02 22:32 ` Heinrich Schuchardt
2025-10-22 3:02 ` Hal Feng
2025-10-22 8:44 ` Hal Feng
2025-08-29 6:09 ` [RFC 05/10] eeprom: starfive: Update eeprom data format version to 3 Hal Feng
2025-08-29 7:47 ` Heinrich Schuchardt
2025-09-02 7:10 ` Hal Feng
2025-09-02 23:29 ` E Shattow
2025-10-22 5:55 ` Hal Feng
2025-08-29 6:09 ` [RFC 06/10] pcie: starfive: Add a optional power gpio support Hal Feng
2025-09-02 23:47 ` E Shattow
2025-10-22 6:13 ` Hal Feng
2025-08-29 6:09 ` [RFC 07/10] riscv: dts: jh7110: Add StarFive VisionFive 2 Lite u-boot device tree Hal Feng
2025-09-03 0:00 ` E Shattow
2025-08-29 6:09 ` [RFC 08/10] configs: visionfive2: Add VisionFive 2 Lite DT to OF_LIST Hal Feng
2025-09-03 0:15 ` E Shattow
2025-10-22 7:12 ` Hal Feng
2025-08-29 6:09 ` [RFC 09/10] board: starfive: spl: Support VisionFive 2 Lite Hal Feng
2025-09-03 0:21 ` E Shattow
2025-08-29 6:09 ` [RFC 10/10] board: starfive: visionfive2: Add VisionFive 2 Lite fdt selection Hal Feng
2025-09-03 0:26 ` E Shattow
2025-09-03 4:34 ` Heinrich Schuchardt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=01a5ff2b-bc20-4670-93ce-2b66df408b96@freeshell.de \
--to=e@freeshell.de \
--cc=emil.renner.berthing@canonical.com \
--cc=hal.feng@starfivetech.com \
--cc=heinrich.schuchardt@canonical.com \
--cc=rick@andestech.com \
--cc=sumit.garg@kernel.org \
--cc=trini@konsulko.com \
--cc=u-boot@lists.denx.de \
--cc=ycliang@andestech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.