Re: Available Arm CPUs with SPE

[Marc Jorda <marc.jorda@bsc.es>]

On 25/11/22 22:06, Al Grant wrote:
> Leo Yan wrote:
>> On Fri, Nov 25, 2022 at 12:17:18PM +0100, Marc Jorda wrote:
>>> Hello,
>>>
>>> I am trying to know which currently available Arm CPUs implement the
>>> Statistical Profiling Extension (SPE), does anyone know where can I
>>> find such information?
>> I don't know we have such kind of info, usually the most safe way is to check
>> SoC vendor's spec and confirm if Arm SPE is supported or not.
>>
>>> As far as I know, it is an optional extension in Armv8.2, but I don't
>>> know if it is mandatory for newer versions. Is it correct to assume
>>> that all Arm Neoverse CPUs have this extension?
>> Yes, since SPE is an optional extension, my understanding is we cannot 100% say
>> SPE is implemented in Armv8.2 and upwards CPUs (though it's unlikely not to
>> implement SPE in Arm standard CPUs).
>>
>> To avoid to mislead you, I would like loop in James and Al for more reliable
>> answer.
> Generally SPE has gone into the server cores but not the mobile cores,
> partly for power/area reasons. Neoverse N1 has SPE, but Cortex-A76,
> which is the same v8.2 architecture and a similar microarchitecture but
> optimized for mobile, does not have SPE. It's not entirely a Neoverse
> vs. Cortex thing though. You can use the PMU event repo to get a list,
> since all CPUs with SPE, and only those, will implement SAMPLE_POP:
>
> $ git clone https://ARM-software/data
> $ grep SAMPLE_POP data/pmu/*
> data/pmu/common_armv8.json:            "name": "SAMPLE_POP",
> data/pmu/common_armv9.json:            "name": "SAMPLE_POP",
> data/pmu/cortex-a715.json:            "name": "SAMPLE_POP",
> data/pmu/cortex-x3.json:            "name": "SAMPLE_POP",
> data/pmu/neoverse-n1.json:            "name": "SAMPLE_POP",
> data/pmu/neoverse-n2.json:            "name": "SAMPLE_POP",
> data/pmu/neoverse-v1.json:            "name": "SAMPLE_POP",
> data/pmu/neoverse-v2.json:            "name": "SAMPLE_POP",
>
> That is believed to be up to date and correct, but to be absolutely sure
> you would need to check the documentation for each core. Third-party
> implementations may also feature SPE, again you would need to check
> documentation. (We'd be happy to include additional PMU event JSON in
> the repo.)
>
> Also, keep in mind that even if SPE is on the CPU, some action is needed
> from firmware, hypervisor OS etc. to make it available to the end user.
> It might or might not be available to a guest OS for example.
>
> Al

Ok, thank you all for the tips, I will check these references.

Regards,
Marc

>
>> Thanks,
>> Leo
> IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

-- 
Accelerators and Communications for HPC
Computer Sciences Department
Barcelona Supercomputing Center (BSC)