From: "Jaehoon Chung" <jh80.chung@samsung.com>
To: "'Judith Mendez'" <jm@ti.com>, "'Peng Fan'" <peng.fan@nxp.com>,
"'Tom Rini'" <trini@konsulko.com>
Cc: "'Nitin Yadav'" <n-yadav@ti.com>,
"'Simon Glass'" <sjg@chromium.org>, <u-boot@lists.denx.de>
Subject: RE: [PATCH 4/5] mmc: am654_sdhci: Set ENDLL=1 for DDR52 mode
Date: Wed, 17 Apr 2024 20:36:55 +0900 [thread overview]
Message-ID: <01fe01da90bb$8d19e6e0$a74db4a0$@samsung.com> (raw)
In-Reply-To: <20240415212747.2678974-5-jm@ti.com>
> -----Original Message-----
> From: Judith Mendez <jm@ti.com>
> Sent: Tuesday, April 16, 2024 6:28 AM
> To: Peng Fan <peng.fan@nxp.com>; Jaehoon Chung <jh80.chung@samsung.com>; Tom Rini <trini@konsulko.com>
> Cc: Nitin Yadav <n-yadav@ti.com>; Simon Glass <sjg@chromium.org>; u-boot@lists.denx.de
> Subject: [PATCH 4/5] mmc: am654_sdhci: Set ENDLL=1 for DDR52 mode
>
> According to the device datasheet [0], ENDLL=1 for
> DDR52 mode, so call am654_sdhci_setup_dll() and write
> itapdly after since we do not carry out tuning.
>
> [0] https://www.ti.com/lit/ds/symlink/am62p.pdf
> Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay")
> Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/am654_sdhci.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
> index 38f1ad28ec4..dee56dfdbaa 100644
> --- a/drivers/mmc/am654_sdhci.c
> +++ b/drivers/mmc/am654_sdhci.c
> @@ -287,12 +287,14 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
>
> regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
>
> - if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) {
> + if ((mode > UHS_SDR25 || mode == MMC_DDR_52) && speed >= CLOCK_TOO_SLOW_HZ) {
> ret = am654_sdhci_setup_dll(plat, speed);
> if (ret)
> return ret;
>
> plat->dll_enable = true;
> + am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
> + plat->itap_del_ena[mode]);
> } else {
> am654_sdhci_setup_delay_chain(plat, mode);
> plat->dll_enable = false;
> --
> 2.43.2
next prev parent reply other threads:[~2024-04-17 11:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 21:27 [PATCH 0/5] Fix MMC tuning algorithm Judith Mendez
2024-04-15 21:27 ` [PATCH 1/5] mmc: am654_sdhci: Add tuning algorithm for delay chain Judith Mendez
2024-04-17 11:23 ` Jaehoon Chung
2024-04-18 14:28 ` Judith Mendez
2024-04-15 21:27 ` [PATCH 2/5] mmc: am654_sdhci: Fix OTAP/ITAP delay values Judith Mendez
2024-04-17 11:28 ` Jaehoon Chung
2024-04-18 14:39 ` Judith Mendez
2024-04-15 21:27 ` [PATCH 3/5] mmc: am654_sdhci: Add itap_del_ena[] to store itapdlyena bit Judith Mendez
2024-04-17 11:34 ` Jaehoon Chung
2024-04-18 14:40 ` Judith Mendez
2024-04-15 21:27 ` [PATCH 4/5] mmc: am654_sdhci: Set ENDLL=1 for DDR52 mode Judith Mendez
2024-04-17 11:36 ` Jaehoon Chung [this message]
2024-04-15 21:27 ` [PATCH 5/5] mmc: am654_sdhci: Fix ITAPDLY for HS400 timing Judith Mendez
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='01fe01da90bb$8d19e6e0$a74db4a0$@samsung.com' \
--to=jh80.chung@samsung.com \
--cc=jm@ti.com \
--cc=n-yadav@ti.com \
--cc=peng.fan@nxp.com \
--cc=sjg@chromium.org \
--cc=trini@konsulko.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.