From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
<intel-gfx@lists.freedesktop.org>,
<intel-xe@lists.freedesktop.org>
Cc: <ville.syrjala@intel.com>
Subject: Re: [PATCH v3 08/15] drm/i915/vrr: Add compute config for DC balance params
Date: Mon, 28 Apr 2025 18:58:27 +0530 [thread overview]
Message-ID: <025998d1-da21-4217-89db-d902cffdb39e@intel.com> (raw)
In-Reply-To: <20250428062058.2811655-9-mitulkumar.ajitkumar.golani@intel.com>
On 4/28/2025 11:50 AM, Mitul Golani wrote:
> Compute DC Balance parameters and tunable params based on
> experiments.
>
> --v2:
> - Document tunable params. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 55923eadc3c1..bc99701be2b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -16,6 +16,13 @@
>
> #define FIXED_POINT_PRECISION 100
> #define CMRR_PRECISION_TOLERANCE 10
> +/*
> + * Tunable parameters for DC Balance correction.
> + * These are captured based on experimentations.
> + */
> +#define DCB_CORRECTION_SENSITIVITY 30
> +#define DCB_CORRECTION_AGGRESSIVENESS 1000
> +#define DCB_BLANK_TARGET 50
>
> bool intel_vrr_is_capable(struct intel_connector *connector)
> {
> @@ -409,6 +416,24 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> (crtc_state->hw.adjusted_mode.crtc_vtotal -
> crtc_state->hw.adjusted_mode.vsync_end);
> }
> +
> + if (HAS_VRR_DC_BALANCE(display) && crtc_state->vrr.dc_balance.enable) {
> + crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
> + crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
> + crtc_state->vrr.dc_balance.max_increase =
> + crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> + crtc_state->vrr.dc_balance.max_decrease =
> + crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> + crtc_state->vrr.dc_balance.guardband =
> + DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax * DCB_CORRECTION_SENSITIVITY,
> + 100);
> + crtc_state->vrr.dc_balance.slope =
> + DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10,
> + crtc_state->vrr.dc_balance.guardband);
> + crtc_state->vrr.dc_balance.vblank_target =
> + DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) * DCB_BLANK_TARGET,
> + 100);
We can make the longer lines more readable with a bit of formatting by
breaking the line after multiplication or at comma:
crtc_state->vrr.dc_balance.guardband =
DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
DCB_CORRECTION_SENSITIVITY, 100);
crtc_state->vrr.dc_balance.slope =
DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10,
crtc_state->vrr.dc_balance.guardband);
crtc_state->vrr.dc_balance.vblank_target =
DIV_ROUND_UP((crtc_state->vrr.vmax -
crtc_state->vrr.vmin) *
DCB_BLANK_TARGET, 100);
Regards,
Ankit
> + }
> }
>
> void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
next prev parent reply other threads:[~2025-04-28 13:29 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-28 6:20 [PATCH v3 00/15] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-04-28 6:20 ` [PATCH v3 01/15] drm/i915/vrr: Fix the adjustment for the fixed rr vtotal for Display < 13 Mitul Golani
2025-04-28 6:20 ` [PATCH v3 02/15] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
2025-04-28 6:20 ` [PATCH v3 03/15] drm/i915/display: Add source param for dc balance Mitul Golani
2025-04-28 12:59 ` Nautiyal, Ankit K
2025-04-28 6:20 ` [PATCH v3 04/15] drm/i915/display: Add registers and bits for DC Balance Mitul Golani
2025-04-28 13:04 ` Nautiyal, Ankit K
2025-04-29 11:20 ` Jani Nikula
2025-04-28 6:20 ` [PATCH v3 05/15] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-04-28 6:20 ` [PATCH v3 06/15] drm/i915/vrr: Add state checker for dc balance params Mitul Golani
2025-04-28 13:08 ` Nautiyal, Ankit K
2025-04-28 6:20 ` [PATCH v3 07/15] drm/i915/vrr: Add state dump " Mitul Golani
2025-04-28 6:20 ` [PATCH v3 08/15] drm/i915/vrr: Add compute config for DC " Mitul Golani
2025-04-28 13:28 ` Nautiyal, Ankit K [this message]
2025-04-28 6:20 ` [PATCH v3 09/15] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-04-28 13:48 ` Nautiyal, Ankit K
2025-04-29 3:12 ` Nautiyal, Ankit K
2025-04-28 6:20 ` [PATCH v3 10/15] drm/i915: Extract vrr_vblank_start() Mitul Golani
2025-04-28 6:20 ` [PATCH v3 11/15] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-04-28 6:20 ` [PATCH v3 12/15] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-04-28 6:20 ` [PATCH v3 13/15] drm/i915/vrr: Restructure VRR enablement bit Mitul Golani
2025-04-29 4:17 ` Nautiyal, Ankit K
2025-04-28 6:20 ` [PATCH v3 14/15] drm/i915/vrr: Pause DC balancing for DSB commits Mitul Golani
2025-04-29 4:20 ` Nautiyal, Ankit K
2025-04-28 6:20 ` [PATCH v3 15/15] drm/i915/vrr: enable dc balance bit Mitul Golani
2025-04-28 6:29 ` ✓ CI.Patch_applied: success for Enable/Disable DC balance along with VRR DSB (rev2) Patchwork
2025-04-28 6:30 ` ✓ CI.checkpatch: " Patchwork
2025-04-28 6:31 ` ✓ CI.KUnit: " Patchwork
2025-04-28 6:39 ` ✓ CI.Build: " Patchwork
2025-04-28 6:41 ` ✓ CI.Hooks: " Patchwork
2025-04-28 6:43 ` ✗ CI.checksparse: warning " Patchwork
2025-04-28 7:32 ` ✓ Xe.CI.BAT: success " Patchwork
2025-04-28 8:42 ` ✗ Xe.CI.Full: failure " Patchwork
2025-04-28 14:46 ` ✗ Fi.CI.SPARSE: warning for Enable/Disable DC balance along with VRR DSB (rev3) Patchwork
2025-04-28 15:07 ` ✗ i915.CI.BAT: failure " Patchwork
2025-05-06 7:05 ` ✓ CI.Patch_applied: success " Patchwork
2025-05-06 7:05 ` ✓ CI.checkpatch: " Patchwork
2025-05-06 7:06 ` ✓ CI.KUnit: " Patchwork
2025-05-06 7:15 ` ✓ CI.Build: " Patchwork
2025-05-06 7:17 ` ✓ CI.Hooks: " Patchwork
2025-05-06 7:18 ` ✗ CI.checksparse: warning " Patchwork
2025-05-06 8:09 ` ✓ Xe.CI.BAT: success " Patchwork
2025-05-06 9:33 ` ✗ Xe.CI.Full: failure " Patchwork
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