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Tue, 18 Mar 2025 12:14:22 -0700 (PDT) Received: from DESKTOPUU50BPD ([2603:6000:a500:306:6d71:de10:2e5e:506a]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c573c4e8b9sm760637585a.2.2025.03.18.12.14.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Mar 2025 12:14:21 -0700 (PDT) From: To: "'Sid Manning'" , "'Brian Cain'" , Cc: , , "'Matheus Bernardino \(QUIC\)'" , , , "'Marco Liebel \(QUIC\)'" , , "'Mark Burton \(QUIC\)'" , "'Brian Cain'" References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> <20250301052845.1012069-6-brian.cain@oss.qualcomm.com> <017101db9763$41ae4ca0$c50ae5e0$@gmail.com> In-Reply-To: Subject: RE: [PATCH 05/39] target/hexagon: Implement modify SSR Date: Tue, 18 Mar 2025 14:14:21 -0500 Message-ID: <026201db9839$f4bb6040$de3220c0$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIWUu77rEigiK0ljjjo9ZdCZqs5mQH/in6LAfNOq9wCQ290DLLSFk3g Content-Language: en-us X-Antivirus: Norton (VPS 250318-4, 3/18/2025), Outbound message X-Antivirus-Status: Clean Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=ltaylorsimpson@gmail.com; helo=mail-qk1-x731.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > -----Original Message----- > From: Sid Manning > Sent: Tuesday, March 18, 2025 1:34 PM > To: ltaylorsimpson@gmail.com; 'Brian Cain' > ; qemu-devel@nongnu.org > Cc: richard.henderson@linaro.org; philmd@linaro.org; Matheus = Bernardino > (QUIC) ; ale@rev.ng; anjo@rev.ng; Marco > Liebel (QUIC) ; alex.bennee@linaro.org; Mark > Burton (QUIC) ; Brian Cain > > Subject: RE: [PATCH 05/39] target/hexagon: Implement modify SSR >=20 >=20 >=20 > > -----Original Message----- > > From: ltaylorsimpson@gmail.com > > Sent: Monday, March 17, 2025 12:37 PM > > To: 'Brian Cain' ; qemu- > devel@nongnu.org > > Cc: richard.henderson@linaro.org; philmd@linaro.org; Matheus > > Bernardino > > (QUIC) ; ale@rev.ng; anjo@rev.ng; Marco > > Liebel (QUIC) ; alex.bennee@linaro.org; = Mark > > Burton (QUIC) ; Sid Manning > > ; Brian Cain > > Subject: RE: [PATCH 05/39] target/hexagon: Implement modify SSR > > > > > -----Original Message----- > > > From: Brian Cain > > > Sent: Friday, February 28, 2025 11:28 PM > > > To: qemu-devel@nongnu.org > > > Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org; > > > philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; > > anjo@rev.ng; > > > quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com; > > > alex.bennee@linaro.org; quic_mburton@quicinc.com; > > sidneym@quicinc.com; > > > Brian Cain > > > Subject: [PATCH 05/39] target/hexagon: Implement modify SSR > > > > > > From: Brian Cain > > > > > > The per-vCPU System Status Register controls many modal behaviors = of > > > the system architecture. When the SSR is updated, we trigger the > > > necessary effects for interrupts, privilege/MMU, and HVX context > > mapping. > > > > > > Signed-off-by: Brian Cain > > > --- > > > > What does SSR_XE indicate? > [Sid Manning] > If SSR:XE isn't set this thread doesn't have the coproc enabled so = discard > additional checking. Any coproc insn issued when ssr:xe is 0 will = trigger a, > "Illegal execution of coprocessor instruction." error. > > > + if (old_XA !=3D new_XA) { > > > + int old_unit =3D parse_context_idx(env, old_XA); > > > + int new_unit =3D parse_context_idx(env, new_XA); > > > > Check that old_unit !=3D new_unit. Per the table above, different = XA values > > can point to the same unit. For example, if cpu->hvx_contexts is 2, = the > XA=3D0 > > and XA=3D2 both point to context 0. > > > > > + > > > + /* Ownership exchange */ > > > + memcpy(VRegs[old_unit], env->VRegs, sizeof(env->VRegs)); > > > + memcpy(QRegs[old_unit], env->QRegs, sizeof(env->QRegs)); > > > + memcpy(env->VRegs, VRegs[new_unit], sizeof(env->VRegs)); > > > + memcpy(env->QRegs, QRegs[new_unit], sizeof(env->QRegs)); > > > > What does the hardware do? Does it clear the context, or is that = the OS'es > > job? > Nothing would keep a single htid from taking hvx unit 0, doing some = hvx-ops > , swapping to hvx unit 1 doing some more hvx-ops and so on. We are = doing > this because each thread has a private copy of the hvx register state. = Since > HVX units and threads are independent if one thread changes its = ownership > from HVX context 0 to HVX context 1 we have to do this copy. Instead = of > memcpy should create a new object that represents the HVX units = available > and change env->VRegs/QRegs to point to the one currently owned. >=20 > Refactoring this will be an improvement. >=20 >=20 > > > > If the hardware leaves the context alone, the above should be > > 1) Copy env->{VQ}Regs to old_unit > > 2) Copy new_unit to env->{VQ}Regs > > > > Should you check SSR_EX before doing these copies? > > > > Do you need to do anything when SSR_EX changes? >=20 > I think you mean SSR:XE before doing the copies. I think we have to = do the > copy here regardless of ssr:xe since a thread could swap ownership, = update > ssr:xa, without explicitly having ssr:xe set. Maybe the OS disables = SSR:XE > while changing hvx unit ownership? Correct. I meant SSR:XE. Some refactoring is in order but need to understand the HW behavior more = specifically. - What will the HW do if more than one thread claims ownership of the = same HVX context? - What happens if a thread claims ownership without setting SSR:XE and = then sets SSR:XE later? - What about this example? 1) Thread 0 claims context 1 and sets SSR:XE 2) Thread 0 does some HVX computation 3) Thread 0 is done with HVX for now so clears SSR:XE 4) Thread 1 claims context 1 and sets SSR:XE, does some work, then = clears SSR:XE 5) Thread 0 wants to do more HVX, so it sets SSR:XE (still pointing = to HVX context 1) We should keep the copies for the contexts and local copies inside = CPUHexagonState. This makes TCG generation easier as well as having = common code between system mode and linux-user mode. Also, since check_overcommitted_hvx only prints a log message, add an = early exit if LOG_GUEST_ERROR is off. Thanks, Taylor