diff for duplicates of <027d01d3854d$3f94aac0$bebe0040$@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 1e795f6..6770f73 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,18 +3,20 @@ This is address in the V2: https://patchwork.kernel.org/patch/10144477/ > -----Original Message----- > From: Julien Thierry [mailto:julien.thierry@arm.com] > Sent: Tuesday, December 12, 2017 5:06 PM -> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk@vger.kernel.org; linux-arm- +> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk@vger.kernel.org; = +linux-arm- > kernel@lists.infradead.org; linux-arm-msm@vger.kernel.org; > sboyd@codeaurora.org > Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; > rnayak@codeaurora.org; will.deacon@arm.com; tfinkel@codeaurora.org; > qualcomm-lt@lists.linaro.org; celster@codeaurora.org; Taniya Das > <tdas@codeaurora.org> -> Subject: Re: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs +> Subject: Re: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha = +PLLs > w/wo dynamic update -> +>=20 > Hi, -> +>=20 > On 12/12/17 12:31, Ilia Lin wrote: > > From: Taniya Das <tdas@codeaurora.org> > > @@ -45,31 +47,33 @@ This is address in the V2: https://patchwork.kernel.org/patch/10144477/ > > return alpha_pll_calc_rate(prate, l, a); > > } > > -> > -static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, +> > -static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long = +rate, > > - unsigned long prate) -> > +static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, +> > +static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long = +rate, > > + unsigned long prate, > > + int (*enable)(struct clk_hw *hw), > > + void (*disable)(struct clk_hw *hw)) > > { > > + bool enabled; -> +>=20 > Some remarks about this. -> -> > struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); +>=20 +> > struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); > > const struct pll_vco *vco; -> > u32 l, off = pll->offset; +> > u32 l, off =3D pll->offset; > > u64 a; > > -> > rate = alpha_pll_round_rate(rate, prate, &l, &a); -> > - vco = alpha_pll_find_vco(pll, rate); +> > rate =3D alpha_pll_round_rate(rate, prate, &l, &a); +> > - vco =3D alpha_pll_find_vco(pll, rate); > > - if (!vco) { > > - pr_err("alpha pll not in a valid vco range\n"); > > - return -EINVAL; -> > + enabled = clk_hw_is_enabled(hw); -> +> > + enabled =3D clk_hw_is_enabled(hw); +>=20 > This is not needed unless we go through the 'else' branch. -> +>=20 > > + > > + if (pll->flags & SUPPORTS_DYNAMIC_UPDATE) { > > + /* @@ -89,7 +93,7 @@ This is address in the V2: https://patchwork.kernel.org/patch/10144477/ > > + if (enabled) > > + disable(hw); > > + -> > + vco = alpha_pll_find_vco(pll, rate); +> > + vco =3D alpha_pll_find_vco(pll, rate); > > + if (!vco) { > > + pr_err("alpha pll not in a valid vco range\n"); > > + return -EINVAL; @@ -101,7 +105,8 @@ This is address in the V2: https://patchwork.kernel.org/patch/10144477/ > > } > > > > regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l); @@ -401,16 -> > +428,29 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned +> > +428,29 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, = +unsigned > long rate, > > regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a > >> 32); @@ -118,39 +123,40 @@ This is address in the V2: https://patchwork.kernel.org/patch/10144477/ > > + if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled) > > + enable(hw); > > + -> -> This condition is only "did we disable the clock and need to reenable it?". -> +>=20 +> This condition is only "did we disable the clock and need to reenable = +it?". +>=20 > To make it clearer, I'd suggest renaming 'enabled' to something like > 'need_reenabling' and the code look like this: -> +>=20 > static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, > unsigned long prate, > int (*enable)(struct clk_hw *hw), > void (*disable)(struct clk_hw *hw)) { -> bool need_reenabling = false; -> +> bool need_reenabling =3D false; +>=20 > [...] -> +>=20 > if(pll->flags & SUPPORTS_DYNAMIC_UPDATE) { > [...] > } else { > if (clk_hw_is_enabled(hw)) { > disable(hw); -> need_reenabling = true; +> need_reenabling =3D true; > } > [...] > } -> +>=20 > [...] -> +>=20 > if (need_reenabling) > enable(hw); -> +>=20 > } -> -> +>=20 +>=20 > Cheers, -> +>=20 > -- > Julien Thierry diff --git a/a/content_digest b/N1/content_digest index c43976f..843cbc2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,17 +5,17 @@ "Subject\0RE: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update\0" "Date\0Thu, 4 Jan 2018 13:14:50 +0200\0" "To\0'Julien Thierry' <julien.thierry@arm.com>" - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-arm-msm@vger.kernel.org - " sboyd@codeaurora.org\0" - "Cc\0mark.rutland@arm.com" - devicetree@vger.kernel.org - rnayak@codeaurora.org - will.deacon@arm.com - tfinkel@codeaurora.org - qualcomm-lt@lists.linaro.org - celster@codeaurora.org + <linux-clk@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + <linux-arm-msm@vger.kernel.org> + " <sboyd@codeaurora.org>\0" + "Cc\0<mark.rutland@arm.com>" + <devicetree@vger.kernel.org> + <rnayak@codeaurora.org> + <will.deacon@arm.com> + <tfinkel@codeaurora.org> + <qualcomm-lt@lists.linaro.org> + <celster@codeaurora.org> " 'Taniya Das' <tdas@codeaurora.org>\0" "\00:1\0" "b\0" @@ -24,18 +24,20 @@ "> -----Original Message-----\n" "> From: Julien Thierry [mailto:julien.thierry@arm.com]\n" "> Sent: Tuesday, December 12, 2017 5:06 PM\n" - "> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk@vger.kernel.org; linux-arm-\n" + "> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk@vger.kernel.org; =\n" + "linux-arm-\n" "> kernel@lists.infradead.org; linux-arm-msm@vger.kernel.org;\n" "> sboyd@codeaurora.org\n" "> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org;\n" "> rnayak@codeaurora.org; will.deacon@arm.com; tfinkel@codeaurora.org;\n" "> qualcomm-lt@lists.linaro.org; celster@codeaurora.org; Taniya Das\n" "> <tdas@codeaurora.org>\n" - "> Subject: Re: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs\n" + "> Subject: Re: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha =\n" + "PLLs\n" "> w/wo dynamic update\n" - "> \n" + ">=20\n" "> Hi,\n" - "> \n" + ">=20\n" "> On 12/12/17 12:31, Ilia Lin wrote:\n" "> > From: Taniya Das <tdas@codeaurora.org>\n" "> >\n" @@ -66,31 +68,33 @@ "> > \treturn alpha_pll_calc_rate(prate, l, a);\n" "> > }\n" "> >\n" - "> > -static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,\n" + "> > -static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long =\n" + "rate,\n" "> > -\t\t\t\t unsigned long prate)\n" - "> > +static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,\n" + "> > +static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long =\n" + "rate,\n" "> > +\t\t\t unsigned long prate,\n" "> > +\t\t\t int (*enable)(struct clk_hw *hw),\n" "> > +\t\t\t void (*disable)(struct clk_hw *hw))\n" "> > {\n" "> > +\tbool enabled;\n" - "> \n" + ">=20\n" "> Some remarks about this.\n" - "> \n" - "> > \tstruct clk_alpha_pll *pll = to_clk_alpha_pll(hw);\n" + ">=20\n" + "> > \tstruct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw);\n" "> > \tconst struct pll_vco *vco;\n" - "> > \tu32 l, off = pll->offset;\n" + "> > \tu32 l, off =3D pll->offset;\n" "> > \tu64 a;\n" "> >\n" - "> > \trate = alpha_pll_round_rate(rate, prate, &l, &a);\n" - "> > -\tvco = alpha_pll_find_vco(pll, rate);\n" + "> > \trate =3D alpha_pll_round_rate(rate, prate, &l, &a);\n" + "> > -\tvco =3D alpha_pll_find_vco(pll, rate);\n" "> > -\tif (!vco) {\n" "> > -\t\tpr_err(\"alpha pll not in a valid vco range\\n\");\n" "> > -\t\treturn -EINVAL;\n" - "> > +\tenabled = clk_hw_is_enabled(hw);\n" - "> \n" + "> > +\tenabled =3D clk_hw_is_enabled(hw);\n" + ">=20\n" "> This is not needed unless we go through the 'else' branch.\n" - "> \n" + ">=20\n" "> > +\n" "> > +\tif (pll->flags & SUPPORTS_DYNAMIC_UPDATE) {\n" "> > +\t\t/*\n" @@ -110,7 +114,7 @@ "> > +\t\tif (enabled)\n" "> > +\t\t\tdisable(hw);\n" "> > +\n" - "> > +\t\tvco = alpha_pll_find_vco(pll, rate);\n" + "> > +\t\tvco =3D alpha_pll_find_vco(pll, rate);\n" "> > +\t\tif (!vco) {\n" "> > +\t\t\tpr_err(\"alpha pll not in a valid vco range\\n\");\n" "> > +\t\t\treturn -EINVAL;\n" @@ -122,7 +126,8 @@ "> > \t}\n" "> >\n" "> > \tregmap_write(pll->clkr.regmap, off + PLL_L_VAL, l); @@ -401,16\n" - "> > +428,29 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned\n" + "> > +428,29 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, =\n" + "unsigned\n" "> long rate,\n" "> > \t\tregmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a\n" "> >> 32);\n" @@ -139,41 +144,42 @@ "> > +\tif (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled)\n" "> > +\t\tenable(hw);\n" "> > +\n" - "> \n" - "> This condition is only \"did we disable the clock and need to reenable it?\".\n" - "> \n" + ">=20\n" + "> This condition is only \"did we disable the clock and need to reenable =\n" + "it?\".\n" + ">=20\n" "> To make it clearer, I'd suggest renaming 'enabled' to something like\n" "> 'need_reenabling' and the code look like this:\n" - "> \n" + ">=20\n" "> static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,\n" "> \t\t\t unsigned long prate,\n" "> \t\t\t int (*enable)(struct clk_hw *hw),\n" "> \t\t\t void (*disable)(struct clk_hw *hw)) {\n" - "> \tbool need_reenabling = false;\n" - "> \n" + "> \tbool need_reenabling =3D false;\n" + ">=20\n" "> \t[...]\n" - "> \n" + ">=20\n" "> \tif(pll->flags & SUPPORTS_DYNAMIC_UPDATE) {\n" "> \t\t[...]\n" "> \t} else {\n" "> \t\tif (clk_hw_is_enabled(hw)) {\n" "> \t\t\tdisable(hw);\n" - "> \t\t\tneed_reenabling = true;\n" + "> \t\t\tneed_reenabling =3D true;\n" "> \t\t}\n" "> \t\t[...]\n" "> \t}\n" - "> \n" + ">=20\n" "> \t[...]\n" - "> \n" + ">=20\n" "> \tif (need_reenabling)\n" "> \t\tenable(hw);\n" - "> \n" + ">=20\n" "> }\n" - "> \n" - "> \n" + ">=20\n" + ">=20\n" "> Cheers,\n" - "> \n" + ">=20\n" "> --\n" > Julien Thierry -671ca3bf9a717b0c8e5f0c8a875722bfb6dba2a13ef18814d53ff40bed3d0a0f +dac2c8cbda64ee13afcdc71efe64c826d2c0e87b6cb3bfd37bccb26b9db46e33
diff --git a/a/1.txt b/N2/1.txt index 1e795f6..8fb367a 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,14 +1,14 @@ This is address in the V2: https://patchwork.kernel.org/patch/10144477/ > -----Original Message----- -> From: Julien Thierry [mailto:julien.thierry@arm.com] +> From: Julien Thierry [mailto:julien.thierry at arm.com] > Sent: Tuesday, December 12, 2017 5:06 PM -> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk@vger.kernel.org; linux-arm- -> kernel@lists.infradead.org; linux-arm-msm@vger.kernel.org; -> sboyd@codeaurora.org -> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; -> rnayak@codeaurora.org; will.deacon@arm.com; tfinkel@codeaurora.org; -> qualcomm-lt@lists.linaro.org; celster@codeaurora.org; Taniya Das +> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk at vger.kernel.org; linux-arm- +> kernel at lists.infradead.org; linux-arm-msm at vger.kernel.org; +> sboyd at codeaurora.org +> Cc: mark.rutland at arm.com; devicetree at vger.kernel.org; +> rnayak at codeaurora.org; will.deacon at arm.com; tfinkel at codeaurora.org; +> qualcomm-lt at lists.linaro.org; celster at codeaurora.org; Taniya Das > <tdas@codeaurora.org> > Subject: Re: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs > w/wo dynamic update diff --git a/a/content_digest b/N2/content_digest index c43976f..882f4ff 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,35 +1,23 @@ "ref\01513081897-31612-1-git-send-email-ilialin@codeaurora.org\0" "ref\01513081897-31612-3-git-send-email-ilialin@codeaurora.org\0" "ref\0ee78b47f-4fdb-01eb-ba04-c1172b7b7b00@arm.com\0" - "From\0<ilialin@codeaurora.org>\0" - "Subject\0RE: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update\0" + "From\0ilialin@codeaurora.org (ilialin at codeaurora.org)\0" + "Subject\0[PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update\0" "Date\0Thu, 4 Jan 2018 13:14:50 +0200\0" - "To\0'Julien Thierry' <julien.thierry@arm.com>" - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-arm-msm@vger.kernel.org - " sboyd@codeaurora.org\0" - "Cc\0mark.rutland@arm.com" - devicetree@vger.kernel.org - rnayak@codeaurora.org - will.deacon@arm.com - tfinkel@codeaurora.org - qualcomm-lt@lists.linaro.org - celster@codeaurora.org - " 'Taniya Das' <tdas@codeaurora.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "This is address in the V2: https://patchwork.kernel.org/patch/10144477/\n" "\n" "> -----Original Message-----\n" - "> From: Julien Thierry [mailto:julien.thierry@arm.com]\n" + "> From: Julien Thierry [mailto:julien.thierry at arm.com]\n" "> Sent: Tuesday, December 12, 2017 5:06 PM\n" - "> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk@vger.kernel.org; linux-arm-\n" - "> kernel@lists.infradead.org; linux-arm-msm@vger.kernel.org;\n" - "> sboyd@codeaurora.org\n" - "> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org;\n" - "> rnayak@codeaurora.org; will.deacon@arm.com; tfinkel@codeaurora.org;\n" - "> qualcomm-lt@lists.linaro.org; celster@codeaurora.org; Taniya Das\n" + "> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk at vger.kernel.org; linux-arm-\n" + "> kernel at lists.infradead.org; linux-arm-msm at vger.kernel.org;\n" + "> sboyd at codeaurora.org\n" + "> Cc: mark.rutland at arm.com; devicetree at vger.kernel.org;\n" + "> rnayak at codeaurora.org; will.deacon at arm.com; tfinkel at codeaurora.org;\n" + "> qualcomm-lt at lists.linaro.org; celster at codeaurora.org; Taniya Das\n" "> <tdas@codeaurora.org>\n" "> Subject: Re: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs\n" "> w/wo dynamic update\n" @@ -176,4 +164,4 @@ "> --\n" > Julien Thierry -671ca3bf9a717b0c8e5f0c8a875722bfb6dba2a13ef18814d53ff40bed3d0a0f +a13b113f3b957872cf45d6bd36554edfb6dc881c50a832ffd3014618205cb8d6
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