From: "Shradha Todi" <shradha.t@samsung.com>
To: manivannan.sadhasivam@linaro.org,
"'Shuai Xue'" <xueshuai@linux.alibaba.com>,
"'Jing Zhang'" <renyu.zj@linux.alibaba.com>,
"'Will Deacon'" <will@kernel.org>,
"'Mark Rutland'" <mark.rutland@arm.com>,
"'Jingoo Han'" <jingoohan1@gmail.com>,
"'Bjorn Helgaas'" <bhelgaas@google.com>,
"'Lorenzo Pieralisi'" <lpieralisi@kernel.org>,
"'Krzysztof Wilczyński'" <kw@linux.com>,
"'Rob Herring'" <robh@kernel.org>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-perf-users@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-arm-msm@vger.kernel.org>
Subject: RE: [PATCH 1/4] perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h'
Date: Thu, 20 Feb 2025 11:31:49 +0530 [thread overview]
Message-ID: <02d901db835c$f0710450$d1530cf0$@samsung.com> (raw)
In-Reply-To: <20250218-pcie-qcom-ptm-v1-1-16d7e480d73e@linaro.org>
> -----Original Message-----
> From: Manivannan Sadhasivam via B4 Relay <devnull+manivannan.sadhasivam.linaro.org@kernel.org>
> Sent: 18 February 2025 20:07
> To: Shuai Xue <xueshuai@linux.alibaba.com>; Jing Zhang <renyu.zj@linux.alibaba.com>; Will Deacon <will@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Jingoo Han <jingoohan1@gmail.com>; Bjorn Helgaas <bhelgaas@google.com>; Lorenzo Pieralisi
> <lpieralisi@kernel.org>; Krzysztof Wilczyński <kw@linux.com>; Rob Herring <robh@kernel.org>
> Cc: Shradha Todi <shradha.t@samsung.com>; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-perf-
> users@vger.kernel.org; linux-pci@vger.kernel.org; linux-arm-msm@vger.kernel.org; Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org>
> Subject: [PATCH 1/4] perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h'
>
> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> Since these are common to all Desginware PCIe IPs, move them to a new header, 'pcie-dwc.h' so that other drivers could make use of
> them.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> MAINTAINERS | 1 +
> drivers/perf/dwc_pcie_pmu.c | 23 ++---------------------
> include/linux/pcie-dwc.h | 34 ++++++++++++++++++++++++++++++++++
> 3 files changed, 37 insertions(+), 21 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 896a307fa065..b4d09d52a750 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -18123,6 +18123,7 @@ S: Maintained
> F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
> F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> F: drivers/pci/controller/dwc/*designware*
> +F: include/linux/pcie-dwc.h
>
> PCI DRIVER FOR TI DRA7XX/J721E
> M: Vignesh Raghavendra <vigneshr@ti.com>
> diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c index cccecae9823f..05b37ea7cf16 100644
> --- a/drivers/perf/dwc_pcie_pmu.c
> +++ b/drivers/perf/dwc_pcie_pmu.c
> @@ -13,6 +13,7 @@
> #include <linux/errno.h>
> #include <linux/kernel.h>
> #include <linux/list.h>
> +#include <linux/pcie-dwc.h>
> #include <linux/perf_event.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> @@ -99,26 +100,6 @@ struct dwc_pcie_dev_info {
> struct list_head dev_node;
> };
>
> -struct dwc_pcie_pmu_vsec_id {
> - u16 vendor_id;
> - u16 vsec_id;
> - u8 vsec_rev;
> -};
> -
> -/*
> - * VSEC IDs are allocated by the vendor, so a given ID may mean different
> - * things to different vendors. See PCIe r6.0, sec 7.9.5.2.
> - */
> -static const struct dwc_pcie_pmu_vsec_id dwc_pcie_pmu_vsec_ids[] = {
> - { .vendor_id = PCI_VENDOR_ID_ALIBABA,
> - .vsec_id = 0x02, .vsec_rev = 0x4 },
> - { .vendor_id = PCI_VENDOR_ID_AMPERE,
> - .vsec_id = 0x02, .vsec_rev = 0x4 },
> - { .vendor_id = PCI_VENDOR_ID_QCOM,
> - .vsec_id = 0x02, .vsec_rev = 0x4 },
> - {} /* terminator */
> -};
> -
> static ssize_t cpumask_show(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -529,7 +510,7 @@ static void dwc_pcie_unregister_pmu(void *data)
>
> static u16 dwc_pcie_des_cap(struct pci_dev *pdev) {
> - const struct dwc_pcie_pmu_vsec_id *vid;
> + const struct dwc_pcie_vsec_id *vid;
> u16 vsec;
> u32 val;
>
> diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h new file mode 100644 index 000000000000..261ae11d75a4
> --- /dev/null
> +++ b/include/linux/pcie-dwc.h
> @@ -0,0 +1,34 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2021-2023 Alibaba Inc.
> + *
> + * Copyright 2025 Linaro Ltd.
> + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> + */
> +
> +#ifndef LINUX_PCIE_DWC_H
> +#define LINUX_PCIE_DWC_H
> +
> +#include <linux/pci_ids.h>
> +
> +struct dwc_pcie_vsec_id {
> + u16 vendor_id;
> + u16 vsec_id;
> + u8 vsec_rev;
> +};
> +
> +/*
> + * VSEC IDs are allocated by the vendor, so a given ID may mean
> +different
> + * things to different vendors. See PCIe r6.0, sec 7.9.5.2.
> + */
> +static const struct dwc_pcie_vsec_id dwc_pcie_pmu_vsec_ids[] = {
Rename this to dwc_pcie_rasdes_vsec_ids? pmu was perf file specific but technically the vsec is rasdes.
> + { .vendor_id = PCI_VENDOR_ID_ALIBABA,
> + .vsec_id = 0x02, .vsec_rev = 0x4 },
> + { .vendor_id = PCI_VENDOR_ID_AMPERE,
> + .vsec_id = 0x02, .vsec_rev = 0x4 },
> + { .vendor_id = PCI_VENDOR_ID_QCOM,
> + .vsec_id = 0x02, .vsec_rev = 0x4 },
> + {} /* terminator */
> +};
> +
> +#endif /* LINUX_PCIE_DWC_H */
>
> --
> 2.25.1
>
next prev parent reply other threads:[~2025-02-20 7:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 14:36 [PATCH 0/4] PCI: dwc: Add PTM sysfs support Manivannan Sadhasivam
2025-02-18 14:36 ` Manivannan Sadhasivam via B4 Relay
2025-02-18 14:36 ` [PATCH 1/4] perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h' Manivannan Sadhasivam
2025-02-18 14:36 ` Manivannan Sadhasivam via B4 Relay
2025-02-18 16:31 ` Dmitry Baryshkov
2025-02-19 7:55 ` Manivannan Sadhasivam
2025-02-20 6:01 ` Shradha Todi [this message]
2025-02-20 7:27 ` Manivannan Sadhasivam
2025-02-18 14:36 ` [PATCH 2/4] PCI: dwc: Add helper to find the Vendor Specific Extended Capability (VSEC) Manivannan Sadhasivam
2025-02-18 14:36 ` Manivannan Sadhasivam via B4 Relay
2025-02-18 14:36 ` [PATCH 3/4] PCI: dwc: Add sysfs support for PTM Manivannan Sadhasivam
2025-02-18 14:36 ` Manivannan Sadhasivam via B4 Relay
2025-02-18 17:54 ` Dmitry Baryshkov
2025-02-19 8:14 ` Manivannan Sadhasivam
2025-02-18 14:36 ` [PATCH 4/4] PCI: qcom-ep: Mask PTM_UPDATING interrupt Manivannan Sadhasivam
2025-02-18 14:36 ` Manivannan Sadhasivam via B4 Relay
2025-02-18 16:17 ` [PATCH 0/4] PCI: dwc: Add PTM sysfs support Frank Li
2025-02-19 7:49 ` Manivannan Sadhasivam
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