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Wed, 19 Mar 2025 14:12:57 -0700 (PDT) Received: from DESKTOPUU50BPD ([2603:6000:a500:306:992d:4509:eca7:6f8]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c573c73273sm905160385a.27.2025.03.19.14.12.56 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Mar 2025 14:12:57 -0700 (PDT) From: To: "'Brian Cain'" , Cc: , , , , , , , , , "'Brian Cain'" References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> <20250301052845.1012069-14-brian.cain@oss.qualcomm.com> In-Reply-To: <20250301052845.1012069-14-brian.cain@oss.qualcomm.com> Subject: RE: [PATCH 13/39] target/hexagon: Implement modify_syscfg() Date: Wed, 19 Mar 2025 16:12:55 -0500 Message-ID: <02db01db9913$afa44b90$0eece2b0$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIWUu77rEigiK0ljjjo9ZdCZqs5mQFIT0Lusvs6OBA= Content-Language: en-us X-Antivirus: Norton (VPS 250319-0, 3/18/2025), Outbound message X-Antivirus-Status: Clean Received-SPF: pass client-ip=2607:f8b0:4864:20::732; envelope-from=ltaylorsimpson@gmail.com; helo=mail-qk1-x732.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > -----Original Message----- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org; > philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng; > quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com; > alex.bennee@linaro.org; quic_mburton@quicinc.com; > sidneym@quicinc.com; Brian Cain > Subject: [PATCH 13/39] target/hexagon: Implement modify_syscfg() > > From: Brian Cain > > Signed-off-by: Brian Cain > --- > target/hexagon/op_helper.c | 51 > +++++++++++++++++++++++++++++++++++++- > 1 file changed, 50 insertions(+), 1 deletion(-) > > diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c > index 03bed11f6e..42805d0f1d 100644 > --- a/target/hexagon/op_helper.c > +++ b/target/hexagon/op_helper.c > @@ -1522,7 +1522,56 @@ static bool > handle_pmu_sreg_write(CPUHexagonState *env, uint32_t reg, > > static void modify_syscfg(CPUHexagonState *env, uint32_t val) { > - g_assert_not_reached(); > + g_assert(bql_locked()); > + > + uint32_t old; > + uint32_t syscfg_read_only_mask = 0x80001c00; > + uint32_t syscfg = arch_get_system_reg(env, HEX_SREG_SYSCFG); > + > + /* clear read-only bits if they are set in the new value. */ > + val &= ~syscfg_read_only_mask; > + /* if read-only are currently set in syscfg keep them set. */ > + val |= (syscfg & syscfg_read_only_mask); > + > + uint32_t tmp = val; > + old = arch_get_system_reg(env, HEX_SREG_SYSCFG); This is the same as syscfg declared above > + arch_set_system_reg(env, HEX_SREG_SYSCFG, tmp); Why is tmp needed? Just use val here. > + > + /* Check for change in MMU enable */ > + target_ulong old_mmu_enable = GET_SYSCFG_FIELD(SYSCFG_MMUEN, > old); > + uint8_t old_en = GET_SYSCFG_FIELD(SYSCFG_PCYCLEEN, old); > + uint8_t old_gie = GET_SYSCFG_FIELD(SYSCFG_GIE, old); > + target_ulong new_mmu_enable = > + GET_SYSCFG_FIELD(SYSCFG_MMUEN, val); Move these declarations to the beginning of the function. > + if (new_mmu_enable && !old_mmu_enable) { > + hex_mmu_on(env); > + } else if (!new_mmu_enable && old_mmu_enable) { > + hex_mmu_off(env); > + } > + > + /* Changing pcycle enable from 0 to 1 resets the counters */ > + uint8_t new_en = GET_SYSCFG_FIELD(SYSCFG_PCYCLEEN, val); > + CPUState *cs; Move the declarations to the beginning of the function > + if (old_en == 0 && new_en == 1) { You could put declaration of cs here if you prefer > + CPU_FOREACH(cs) { > + CPUHexagonState *_env = cpu_env(cs); > + _env->t_cycle_count = 0; I'm not a fan of _env as a variable name. Just do cpu_env(cs)->t_cycle_count = 0 > + } > + } > + > + /* See if global interrupts are turned on */ > + uint8_t new_gie = GET_SYSCFG_FIELD(SYSCFG_GIE, val); Move the declaration to the beginning > + if (!old_gie && new_gie) { > + qemu_log_mask(CPU_LOG_INT, "%s: global interrupts enabled\n", > __func__); > + hex_interrupt_update(env); > + } > + > + if (qemu_loglevel_mask(LOG_UNIMP)) { > + int new_v2x = GET_SYSCFG_FIELD(SYSCFG_V2X, val); > + if (!new_v2x) { > + qemu_log("HVX: 64 byte vector length is unsupported\n"); > + } > + } > } > > static uint32_t hexagon_find_last_irq(CPUHexagonState *env, uint32_t vid) > -- > 2.34.1