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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429ce80ded1sm10663397f8f.4.2025.11.03.08.25.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Nov 2025 08:25:54 -0800 (PST) Message-ID: <02ee0143-1da2-4e71-af50-b1dc2b920c05@redhat.com> Date: Mon, 3 Nov 2025 17:25:52 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 26/32] hw/arm/smmuv3-accel: Add a property to specify RIL support To: Shameer Kolothum , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , Jason Gunthorpe , Nicolin Chen , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , Krishnakant Jaju References: <20251031105005.24618-1-skolothumtho@nvidia.com> <20251031105005.24618-27-skolothumtho@nvidia.com> <2e8bd9fe-2434-443e-ae4e-e15352ff112a@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: D8-8Oiqvn7u68yuAKmxeWkFKy946kJ-HTV0laSYi63E_1762187155 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 11/3/25 5:08 PM, Shameer Kolothum wrote: > Hi Eric, > >> -----Original Message----- >> From: Eric Auger >> Sent: 03 November 2025 15:07 >> To: Shameer Kolothum ; qemu- >> arm@nongnu.org; qemu-devel@nongnu.org >> Cc: peter.maydell@linaro.org; Jason Gunthorpe ; Nicolin >> Chen ; ddutile@redhat.com; berrange@redhat.com; >> Nathan Chen ; Matt Ochs ; >> smostafa@google.com; wangzhou1@hisilicon.com; >> jiangkunkun@huawei.com; jonathan.cameron@huawei.com; >> zhangfei.gao@linaro.org; zhenzhong.duan@intel.com; yi.l.liu@intel.com; >> Krishnakant Jaju >> Subject: Re: [PATCH v5 26/32] hw/arm/smmuv3-accel: Add a property to >> specify RIL support >> >> External email: Use caution opening links or attachments >> >> >> Hi Shameer, >> >> On 10/31/25 11:49 AM, Shameer Kolothum wrote: >>> Currently QEMU SMMUv3 has RIL support by default. But if accelerated >>> mode is enabled, RIL has to be compatible with host SMMUv3 support. >>> >>> Add a property so that the user can specify this. >>> >>> Reviewed-by: Jonathan Cameron >>> Tested-by: Zhangfei Gao >>> Signed-off-by: Shameer Kolothum >> I have not seen any reply on >> https://lore.kernel.org/all/b6105534-4a17-4700-bb0b- >> e961babd10bb@redhat.com/ > Sorry, looks like I missed to reply. > >> I guess you chose to restrict RIL to accel only. > Yes. I have updated the description. > > About AIDR consistency check, >> did you have a look? > I have added that check in patch #19. But Zhangfei has reported a problem > with that as his hardware reports AIDR = 0. . Please take a look that > discussion. OK Thanks. I still think it may be relevant to support disabling RIL for non accel mode but this can be added later on. feel free to add my Reviewed-by: Eric Auger Eric > > Thanks, > Shameer >