Re: [PATCH v2] renesas: Renesas R-Car Gen4 watchdog driver

[Marek Vasut <marek.vasut@mailbox.org>]

On 5/30/25 12:58 AM, Shmuel Melamud via B4 Relay wrote:
> From: Shmuel Melamud <smelamud@redhat.com>
> 
> Add support of Renesas R-Car Gen4 watchdog timer. Timeouts up to
> 8184.0s are supported (CKS1 register is not involved). The watchdog
> uses the clock type CLK_TYPE_GEN4_MDSEL, so handling of this constant
> is added to gen3_clk_get_rate64() function.
> 
> The timeout is set in
> dts/upstream/src/arm64/renesas/r8a779f0-spider-cpu.dtsi section &rwdt.
> 
> This patch was tested on real Renesas R8A779F0 hardware. If the watchdog
> driver is enabled at the build time, the watchdog timer is initialized
> when U-Boot starts. Under normal circumstances, U-Boot loads the kernel,
> it starts systemd and systemd continues to pet the watchdog. If systemd
> is not started before the timeout expires, the watchdog resets the
> board.
> 
> Signed-off-by: Shmuel Leib Melamud <smelamud@redhat.com>
> ---
>   drivers/clk/renesas/clk-rcar-gen3.c |   4 +-
>   drivers/watchdog/Kconfig            |   8 ++
>   drivers/watchdog/Makefile           |   1 +
>   drivers/watchdog/renesas_wdt.c      | 172 ++++++++++++++++++++++++++++++++++++
>   4 files changed, 184 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
> index 375cc4a4930873ad0d5509c19ad04a0ea5545aa0..5745acf4023c9114f6fa13b5e4baa306c5b57d33 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -68,7 +68,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
>   		if (ret)
>   			return ret;
>   
> -		if (core->type == CLK_TYPE_GEN3_MDSEL) {
> +		if (core->type == CLK_TYPE_GEN3_MDSEL || core->type == CLK_TYPE_GEN4_MDSEL) {
>   			shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
>   			parent->dev = clk->dev;
>   			parent->id = core->parent >> shift;
> @@ -318,6 +318,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
>   						"FIXED");
>   
>   	case CLK_TYPE_GEN3_MDSEL:
> +		fallthrough;
> +	case CLK_TYPE_GEN4_MDSEL:
>   		shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
>   		div = (core->div >> shift) & 0xffff;
>   		rate = gen3_clk_get_rate64(&parent) / div;

Clock driver change should be in separate patch.

I'll try to review the watchdog driver itself in the next few days.

Thanks !