From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH 16/20] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
Date: Mon, 4 Sep 2023 11:21:44 -0300 [thread overview]
Message-ID: <04487f2f-3fc9-7bc3-1083-9f6328a18925@ventanamicro.com> (raw)
In-Reply-To: <20230831-9135d7f6e2059b82be3f9300@orel>
On 8/31/23 09:01, Andrew Jones wrote:
> On Fri, Aug 25, 2023 at 10:08:49AM -0300, Daniel Henrique Barboza wrote:
>> All code related to MISA TCG properties is also moved.
>>
>> At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
>> properties handling is done in kvm-cpu.c.
>>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/cpu.c | 89 --------------------------------------
>> target/riscv/cpu.h | 1 -
>> target/riscv/tcg/tcg-cpu.c | 84 +++++++++++++++++++++++++++++++++++
>> 3 files changed, 84 insertions(+), 90 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 89b09a7e89..3c9db46837 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -1201,49 +1201,6 @@ static void riscv_cpu_init(Object *obj)
>> #endif /* CONFIG_USER_ONLY */
>> }
>>
>> -typedef struct RISCVCPUMisaExtConfig {
>> - const char *name;
>> - const char *description;
>> - target_ulong misa_bit;
>> - bool enabled;
>> -} RISCVCPUMisaExtConfig;
>> -
>> -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
>> - void *opaque, Error **errp)
>> -{
>> - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
>> - target_ulong misa_bit = misa_ext_cfg->misa_bit;
>> - RISCVCPU *cpu = RISCV_CPU(obj);
>> - CPURISCVState *env = &cpu->env;
>> - bool value;
>> -
>> - if (!visit_type_bool(v, name, &value, errp)) {
>> - return;
>> - }
>> -
>> - if (value) {
>> - env->misa_ext |= misa_bit;
>> - env->misa_ext_mask |= misa_bit;
>> - } else {
>> - env->misa_ext &= ~misa_bit;
>> - env->misa_ext_mask &= ~misa_bit;
>> - }
>> -}
>> -
>> -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
>> - void *opaque, Error **errp)
>> -{
>> - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
>> - target_ulong misa_bit = misa_ext_cfg->misa_bit;
>> - RISCVCPU *cpu = RISCV_CPU(obj);
>> - CPURISCVState *env = &cpu->env;
>> - bool value;
>> -
>> - value = env->misa_ext & misa_bit;
>> -
>> - visit_type_bool(v, name, &value, errp);
>> -}
>> -
>> typedef struct misa_ext_info {
>> const char *name;
>> const char *description;
>> @@ -1304,52 +1261,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
>> return val;
>> }
>>
>> -#define MISA_CFG(_bit, _enabled) \
>> - {.misa_bit = _bit, .enabled = _enabled}
>> -
>> -static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>> - MISA_CFG(RVA, true),
>> - MISA_CFG(RVC, true),
>> - MISA_CFG(RVD, true),
>> - MISA_CFG(RVF, true),
>> - MISA_CFG(RVI, true),
>> - MISA_CFG(RVE, false),
>> - MISA_CFG(RVM, true),
>> - MISA_CFG(RVS, true),
>> - MISA_CFG(RVU, true),
>> - MISA_CFG(RVH, true),
>> - MISA_CFG(RVJ, false),
>> - MISA_CFG(RVV, false),
>> - MISA_CFG(RVG, false),
>> -};
>> -
>> -void riscv_cpu_add_misa_properties(Object *cpu_obj)
>> -{
>> - int i;
>> -
>> - for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
>> - RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
>> - int bit = misa_cfg->misa_bit;
>> -
>> - misa_cfg->name = riscv_get_misa_ext_name(bit);
>> - misa_cfg->description = riscv_get_misa_ext_description(bit);
>> -
>> - /* Check if KVM already created the property */
>> - if (object_property_find(cpu_obj, misa_cfg->name)) {
>> - continue;
>> - }
>> -
>> - object_property_add(cpu_obj, misa_cfg->name, "bool",
>> - cpu_get_misa_ext_cfg,
>> - cpu_set_misa_ext_cfg,
>> - NULL, (void *)misa_cfg);
>> - object_property_set_description(cpu_obj, misa_cfg->name,
>> - misa_cfg->description);
>> - object_property_set_bool(cpu_obj, misa_cfg->name,
>> - misa_cfg->enabled, NULL);
>> - }
>> -}
>> -
>> #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
>> {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
>> .enabled = _defval}
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 74fbb33e09..4269523e24 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
>> extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
>> extern Property riscv_cpu_options[];
>>
>> -void riscv_cpu_add_misa_properties(Object *cpu_obj);
>> void riscv_add_satp_mode_properties(Object *obj);
>>
>> /* CSR function table */
>> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
>> index 68ce3cbcb9..8e3f55d3a6 100644
>> --- a/target/riscv/tcg/tcg-cpu.c
>> +++ b/target/riscv/tcg/tcg-cpu.c
>> @@ -574,6 +574,90 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
>> return true;
>> }
>>
>> +typedef struct RISCVCPUMisaExtConfig {
>> + const char *name;
>> + const char *description;
>> + target_ulong misa_bit;
>> + bool enabled;
>> +} RISCVCPUMisaExtConfig;
>> +
>> +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
>> + void *opaque, Error **errp)
>> +{
>> + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
>> + target_ulong misa_bit = misa_ext_cfg->misa_bit;
>> + RISCVCPU *cpu = RISCV_CPU(obj);
>> + CPURISCVState *env = &cpu->env;
>> + bool value;
>> +
>> + if (!visit_type_bool(v, name, &value, errp)) {
>> + return;
>> + }
>> +
>> + if (value) {
>> + env->misa_ext |= misa_bit;
>> + env->misa_ext_mask |= misa_bit;
>> + } else {
>> + env->misa_ext &= ~misa_bit;
>> + env->misa_ext_mask &= ~misa_bit;
>> + }
>> +}
>> +
>> +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
>> + void *opaque, Error **errp)
>> +{
>> + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
>> + target_ulong misa_bit = misa_ext_cfg->misa_bit;
>> + RISCVCPU *cpu = RISCV_CPU(obj);
>> + CPURISCVState *env = &cpu->env;
>> + bool value;
>> +
>> + value = env->misa_ext & misa_bit;
>> +
>> + visit_type_bool(v, name, &value, errp);
>> +}
>> +
>> +#define MISA_CFG(_bit, _enabled) \
>> + {.misa_bit = _bit, .enabled = _enabled}
>> +
>> +static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>
> Can this be const?
At this moment it can't because we're setting 'name' and 'description' for
each element down there in riscv_cpu_add_misa_properties().
However, in a quick look it seems that we don't need these fields because we
don't access 'name' or 'description' using the struct after the property is
created.
I'll take another look and, if that's indeed the case, I'll do a prep patch
to make these changes before moving code in this patch. Thanks,
Daniel
>
>> + MISA_CFG(RVA, true),
>> + MISA_CFG(RVC, true),
>> + MISA_CFG(RVD, true),
>> + MISA_CFG(RVF, true),
>> + MISA_CFG(RVI, true),
>> + MISA_CFG(RVE, false),
>> + MISA_CFG(RVM, true),
>> + MISA_CFG(RVS, true),
>> + MISA_CFG(RVU, true),
>> + MISA_CFG(RVH, true),
>> + MISA_CFG(RVJ, false),
>> + MISA_CFG(RVV, false),
>> + MISA_CFG(RVG, false),
>> +};
>> +
>> +static void riscv_cpu_add_misa_properties(Object *cpu_obj)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
>> + RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
>> + int bit = misa_cfg->misa_bit;
>> +
>> + misa_cfg->name = riscv_get_misa_ext_name(bit);
>> + misa_cfg->description = riscv_get_misa_ext_description(bit);
>> +
>> + object_property_add(cpu_obj, misa_cfg->name, "bool",
>> + cpu_get_misa_ext_cfg,
>> + cpu_set_misa_ext_cfg,
>> + NULL, (void *)misa_cfg);
>> + object_property_set_description(cpu_obj, misa_cfg->name,
>> + misa_cfg->description);
>> + object_property_set_bool(cpu_obj, misa_cfg->name,
>> + misa_cfg->enabled, NULL);
>> + }
>> +}
>> +
>> static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
>> void *opaque, Error **errp)
>> {
>> --
>> 2.41.0
>>
>>
>
> Otherwise,
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-09-04 14:22 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 13:08 [PATCH 00/20] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 01/20] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
2023-08-31 10:17 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 02/20] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
2023-08-31 10:21 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 03/20] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
2023-08-31 10:31 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 04/20] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
2023-08-28 16:30 ` Philippe Mathieu-Daudé
2023-08-31 10:38 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 05/20] target/riscv/cpu.c: add 'user_extension_properties' class prop Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 06/20] target/riscv: add 'max_features' CPU flag Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 07/20] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
2023-08-31 11:00 ` Andrew Jones
2023-09-01 20:08 ` Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 08/20] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
2023-08-28 16:35 ` Philippe Mathieu-Daudé
2023-08-31 11:04 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 09/20] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
2023-08-31 11:10 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 10/20] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
2023-08-31 11:22 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 11/20] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
2023-08-28 16:38 ` Philippe Mathieu-Daudé
2023-08-29 13:16 ` Daniel Henrique Barboza
2023-08-31 11:26 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 12/20] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
2023-08-28 16:47 ` Philippe Mathieu-Daudé
2023-08-30 18:21 ` Daniel Henrique Barboza
2023-08-30 20:54 ` Philippe Mathieu-Daudé
2023-08-31 11:30 ` Andrew Jones
2023-09-01 17:19 ` Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 13/20] target/riscv/kvm: refactor kvm_riscv_init_user_properties() Daniel Henrique Barboza
2023-08-31 11:34 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 14/20] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-08-31 11:50 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 15/20] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
2023-08-31 11:56 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 16/20] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
2023-08-31 12:01 ` Andrew Jones
2023-09-04 14:21 ` Daniel Henrique Barboza [this message]
2023-08-25 13:08 ` [PATCH 17/20] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
2023-08-31 12:06 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 18/20] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
2023-08-31 12:07 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 19/20] target/riscv: add 'tcg_supported' class property Daniel Henrique Barboza
2023-08-31 12:25 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 20/20] target/riscv: add 'kvm_supported' " Daniel Henrique Barboza
2023-08-31 12:47 ` Andrew Jones
2023-09-01 20:57 ` Daniel Henrique Barboza
2023-09-04 9:05 ` Andrew Jones
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