From: "Khatri, Sunil" <sukhatri@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>,
Alex Deucher <alexander.deucher@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs
Date: Mon, 7 Apr 2025 15:44:30 +0530 [thread overview]
Message-ID: <04635121-c8ca-42ba-a56b-20357702c929@amd.com> (raw)
In-Reply-To: <CADnq5_O1TWAx9neJmNtAQ+kmn+85NHsfzoMr5P_fbz=ZRNpoHw@mail.gmail.com>
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On 3/25/2025 1:18 AM, Alex Deucher wrote:
> ping on this series?
>
> Alex
>
> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher<alexander.deucher@amd.com> wrote:
>> In dev core dump, dump the full header fifo for
>> each queue. Each FIFO has 8 entries.
>>
>> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
>> 1 file changed, 49 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index f4dfa1418b740..64342160ff7d0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>> - /* cp header registers */
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> /* SE status registers */
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
>> + /* packet headers */
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
Reading this register in a loop will give value of each queue or we are
reading same register again and again ?
for(i=0; i<reg_count; i++)
adev->gfx.ip_dump_core[i]
=RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); With above loop arent
we reading same offset again for
mmCP_CE_HEADER_DUMP,mmCP_PFP_HEADER_DUMP and mmCP_ME_HEADER_DUMP 8 times. How are we making sure we are reading from different queues ?
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
>> };
>>
>> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
>> };
>>
>> enum ta_ras_gfx_subblock {
>> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer
>> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
>> drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
>> for (reg = 0; reg < reg_count; reg++) {
>> - drm_printf(p, "%-50s \t 0x%08x\n",
>> - gc_cp_reg_list_9[reg].reg_name,
>> - adev->gfx.ip_dump_compute_queues[index + reg]);
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + "mmCP_MEC_ME2_HEADER_DUMP",
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> + else
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + gc_cp_reg_list_9[reg].reg_name,
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> }
>> index += reg_count;
>> }
>> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)
>> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>>
>> for (reg = 0; reg < reg_count; reg++) {
>> - adev->gfx.ip_dump_compute_queues[index + reg] =
>> - RREG32(SOC15_REG_ENTRY_OFFSET(
>> - gc_cp_reg_list_9[reg]));
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
>> + else
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_ENTRY_OFFSET(
>> + gc_cp_reg_list_9[reg]));
When value of (i != 0), arent we reading same register i.e
mmCP_MEC_ME1_HEADER_DUMP 8 times, how are we making sure when we read it
again its reading for another queue ?
Regards
Sunil Khatri
>> }
>> index += reg_count;
>> }
>> --
>> 2.49.0
>>
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next prev parent reply other threads:[~2025-04-07 10:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 16:56 [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs Alex Deucher
2025-03-20 16:56 ` [PATCH 2/5] drm/amdgpu/gfx9.4.3: " Alex Deucher
2025-03-20 16:56 ` [PATCH 3/5] drm/amdgpu/gfx10: " Alex Deucher
2025-03-20 16:56 ` [PATCH 4/5] drm/amdgpu/gfx11: " Alex Deucher
2025-03-20 16:56 ` [PATCH 5/5] drm/amdgpu/gfx12: " Alex Deucher
2025-03-24 19:48 ` [PATCH 1/5] drm/amdgpu/gfx9: " Alex Deucher
2025-04-07 8:50 ` Pierre-Eric Pelloux-Prayer
2025-04-07 10:14 ` Khatri, Sunil [this message]
2025-04-07 12:56 ` Alex Deucher
2025-04-07 13:27 ` Khatri, Sunil
2025-04-07 13:45 ` Alex Deucher
2025-04-07 14:00 ` Khatri, Sunil
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