Re: [RFC PATCH 35/38] target/riscv: Add implied rules for Zvfbdota32f extension

[Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvfbdota32f
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ed0f5ed976a..ff09bafe667 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2903,6 +2903,15 @@ static RISCVCPUImpliedExtsRule ZVFQWBDOTA8F_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVFBDOTA32F_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfbdota32f),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
>       .implied_multi_exts = {
> @@ -3131,6 +3140,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVE64D_IMPLIED,
>       &ZVE64F_IMPLIED,
>       &ZVE64X_IMPLIED,
> +    &ZVFBDOTA32F_IMPLIED,
>       &ZVFBFA_IMPLIED,
>       &ZVFBFMIN_IMPLIED,
>       &ZVFBFWMA_IMPLIED,