From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A27CC433DF for ; Thu, 2 Jul 2020 16:05:23 +0000 (UTC) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 59862207CD for ; Thu, 2 Jul 2020 16:05:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 59862207CD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 2A1388AFEC; Thu, 2 Jul 2020 16:05:23 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9vShlsnJDvX7; Thu, 2 Jul 2020 16:05:22 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by whitealder.osuosl.org (Postfix) with ESMTP id 5E1ED8AFDF; Thu, 2 Jul 2020 16:05:22 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 44409C0888; Thu, 2 Jul 2020 16:05:22 +0000 (UTC) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by lists.linuxfoundation.org (Postfix) with ESMTP id 68D82C0733 for ; Thu, 2 Jul 2020 16:05:20 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 562FB8AFDF for ; Thu, 2 Jul 2020 16:05:20 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qAylt0h6p78T for ; Thu, 2 Jul 2020 16:05:19 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by whitealder.osuosl.org (Postfix) with ESMTP id F1FEB8AFE2 for ; Thu, 2 Jul 2020 16:05:18 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DD53C1FB; Thu, 2 Jul 2020 09:05:17 -0700 (PDT) Received: from [10.57.21.32] (unknown [10.57.21.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D70973F71E; Thu, 2 Jul 2020 09:05:14 -0700 (PDT) Subject: Re: [PATCH v8 2/3] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU To: Krishna Reddy , Jonathan Hunter References: <20200630001051.12350-1-vdumpa@nvidia.com> <20200630001051.12350-3-vdumpa@nvidia.com> <3e655881-bac4-f083-44ed-cfa0a61298d0@arm.com> <0d4f46d6-6a4e-bca0-bcf3-0e22a950e57b@nvidia.com> From: Robin Murphy Message-ID: <04e35d51-5e65-047d-90ef-a2de901eb15d@arm.com> Date: Thu, 2 Jul 2020 17:05:05 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-GB Cc: Sachin Nikam , "nicoleotsuka@gmail.com" , Mikko Perttunen , Bryan Huntsman , "linux-kernel@vger.kernel.org" , Pritesh Raithatha , Timo Alho , "iommu@lists.linux-foundation.org" , Nicolin Chen , "linux-tegra@vger.kernel.org" , Yu-Huan Hsu , Thierry Reding , "will@kernel.org" , "linux-arm-kernel@lists.infradead.org" , Bitan Biswas X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2020-07-01 20:39, Krishna Reddy wrote: > On 01/07/2020 20:00, Krishna Reddy wrote: >>>>>>> + items: >>>>>>> + - enum: >>>>>>> + - nvdia,tegra194-smmu >>>>>>> + - const: arm,mmu-500 >>>>> >>>>>> Is the fallback compatible appropriate here? If software treats this as a standard MMU-500 it will only program the first instance (because the second isn't presented as a separate MMU-500) - is there any way that isn't going to blow up? >>>>> >>>>> When compatible is set to both nvidia,tegra194-smmu and arm,mmu-500, implementation override ensure that both instances are programmed. Isn't it? I am not sure I follow your comment fully. >>> >>>> The problem is, if for some reason someone had a Tegra194, but only set the compatible string to 'arm,mmu-500' it would assume that it was a normal arm,mmu-500 and only one instance would be programmed. We always want at least 2 of the 3 instances >>programmed and so we should only match 'nvidia,tegra194-smmu'. In fact, I think that we also need to update the arm_smmu_of_match table to add 'nvidia,tegra194-smmu' with the data set to &arm_mmu500. >>> >>> In that case, new binding "nvidia,smmu-v2" can be added with data set to &arm_mmu500 and enumeration would have nvidia,tegra194-smmu and another variant for next generation SoC in future. > >> I think you would be better off with nvidia,smmu-500 as smmu-v2 appears to be something different. I see others have a smmu-v2 but I am not sure if that is legacy. We have an smmu-500 and so that would seem more appropriate. > > I tried to use the binding synonymous to other vendors. > V2 is the architecture version. MMU-500 is the actual implementation from ARM based on V2 arch. As we just use the MMU-500 IP as it is, It can be named as nvidia,smmu-500 or similar as well. Yup, that sounds OK to me if you want a broader compatible to potentially match other future SoCs as well. > Others probably having their own implementation based on V2 arch. Exactly - "cavium,smmu-v2" and "qcom,smmu-v2" are their own in-house microarchitectures, not one of Arm's designs, so they don't really have a suitable 'product name' we could have used for the bindings. Robin. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 From: Robin Murphy Subject: Re: [PATCH v8 2/3] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU Date: Thu, 2 Jul 2020 17:05:05 +0100 Message-ID: <04e35d51-5e65-047d-90ef-a2de901eb15d@arm.com> References: <20200630001051.12350-1-vdumpa@nvidia.com> <20200630001051.12350-3-vdumpa@nvidia.com> <3e655881-bac4-f083-44ed-cfa0a61298d0@arm.com> <0d4f46d6-6a4e-bca0-bcf3-0e22a950e57b@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-GB Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Krishna Reddy , Jonathan Hunter Cc: "joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org" , "will-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Thierry Reding , Yu-Huan Hsu , Sachin Nikam , Pritesh Raithatha , Timo Alho , Bitan Biswas , Mikko Perttunen , Nicolin Chen , Bryan Huntsman , "nicoleotsuka-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" List-Id: linux-tegra@vger.kernel.org On 2020-07-01 20:39, Krishna Reddy wrote: > On 01/07/2020 20:00, Krishna Reddy wrote: >>>>>>> + items: >>>>>>> + - enum: >>>>>>> + - nvdia,tegra194-smmu >>>>>>> + - const: arm,mmu-500 >>>>> >>>>>> Is the fallback compatible appropriate here? If software treats this as a standard MMU-500 it will only program the first instance (because the second isn't presented as a separate MMU-500) - is there any way that isn't going to blow up? >>>>> >>>>> When compatible is set to both nvidia,tegra194-smmu and arm,mmu-500, implementation override ensure that both instances are programmed. Isn't it? I am not sure I follow your comment fully. >>> >>>> The problem is, if for some reason someone had a Tegra194, but only set the compatible string to 'arm,mmu-500' it would assume that it was a normal arm,mmu-500 and only one instance would be programmed. We always want at least 2 of the 3 instances >>programmed and so we should only match 'nvidia,tegra194-smmu'. In fact, I think that we also need to update the arm_smmu_of_match table to add 'nvidia,tegra194-smmu' with the data set to &arm_mmu500. >>> >>> In that case, new binding "nvidia,smmu-v2" can be added with data set to &arm_mmu500 and enumeration would have nvidia,tegra194-smmu and another variant for next generation SoC in future. > >> I think you would be better off with nvidia,smmu-500 as smmu-v2 appears to be something different. I see others have a smmu-v2 but I am not sure if that is legacy. We have an smmu-500 and so that would seem more appropriate. > > I tried to use the binding synonymous to other vendors. > V2 is the architecture version. MMU-500 is the actual implementation from ARM based on V2 arch. As we just use the MMU-500 IP as it is, It can be named as nvidia,smmu-500 or similar as well. Yup, that sounds OK to me if you want a broader compatible to potentially match other future SoCs as well. > Others probably having their own implementation based on V2 arch. Exactly - "cavium,smmu-v2" and "qcom,smmu-v2" are their own in-house microarchitectures, not one of Arm's designs, so they don't really have a suitable 'product name' we could have used for the bindings. Robin. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FA48C433E0 for ; Thu, 2 Jul 2020 16:07:00 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2E6892068F for ; Thu, 2 Jul 2020 16:07:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uBwy8z8a" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2E6892068F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DQ3MqC+tI7NZWko4cwDHhqMzMB8LtYbU/pQAOZXycdg=; b=uBwy8z8aNivMSRQob6ZLGggRw AgBGqGvzm4VPNhYtAGul1Eylucy+KgFmAGuBkzFILIeuH/vzZLCAArIqEZxQggzoI1ayF9E7pzKQl fEz1wNWWbM3GXO8LJicci9DTb2eZXiM3PuIjIALOX6NTa9onFkvDzn2oWKsgmHajOcZYzhWc+VJK/ l3PDMAXvOkrosHsfv8kbLjcZq5aAV9eBVqkf4qjy492Lfyh6PxvOkde3iHoiV1Tehx7xA3Psuj/1P qYN93zi3IKMsiwe33L+Q+vGOhnRPuoER7lnEV7x8UrLXwtIaiLdDdHPKoesc8I3zSTgpKcsSVG/By 3NRuks0iQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jr1iF-0006b2-LW; Thu, 02 Jul 2020 16:05:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jr1iC-0006aB-Rd for linux-arm-kernel@lists.infradead.org; Thu, 02 Jul 2020 16:05:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DD53C1FB; Thu, 2 Jul 2020 09:05:17 -0700 (PDT) Received: from [10.57.21.32] (unknown [10.57.21.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D70973F71E; Thu, 2 Jul 2020 09:05:14 -0700 (PDT) Subject: Re: [PATCH v8 2/3] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU To: Krishna Reddy , Jonathan Hunter References: <20200630001051.12350-1-vdumpa@nvidia.com> <20200630001051.12350-3-vdumpa@nvidia.com> <3e655881-bac4-f083-44ed-cfa0a61298d0@arm.com> <0d4f46d6-6a4e-bca0-bcf3-0e22a950e57b@nvidia.com> From: Robin Murphy Message-ID: <04e35d51-5e65-047d-90ef-a2de901eb15d@arm.com> Date: Thu, 2 Jul 2020 17:05:05 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_120520_995961_D6083BD9 X-CRM114-Status: GOOD ( 17.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sachin Nikam , "nicoleotsuka@gmail.com" , Mikko Perttunen , Bryan Huntsman , "joro@8bytes.org" , "linux-kernel@vger.kernel.org" , Pritesh Raithatha , Timo Alho , "iommu@lists.linux-foundation.org" , Nicolin Chen , "linux-tegra@vger.kernel.org" , Yu-Huan Hsu , Thierry Reding , "will@kernel.org" , "linux-arm-kernel@lists.infradead.org" , Bitan Biswas Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-07-01 20:39, Krishna Reddy wrote: > On 01/07/2020 20:00, Krishna Reddy wrote: >>>>>>> + items: >>>>>>> + - enum: >>>>>>> + - nvdia,tegra194-smmu >>>>>>> + - const: arm,mmu-500 >>>>> >>>>>> Is the fallback compatible appropriate here? If software treats this as a standard MMU-500 it will only program the first instance (because the second isn't presented as a separate MMU-500) - is there any way that isn't going to blow up? >>>>> >>>>> When compatible is set to both nvidia,tegra194-smmu and arm,mmu-500, implementation override ensure that both instances are programmed. Isn't it? I am not sure I follow your comment fully. >>> >>>> The problem is, if for some reason someone had a Tegra194, but only set the compatible string to 'arm,mmu-500' it would assume that it was a normal arm,mmu-500 and only one instance would be programmed. We always want at least 2 of the 3 instances >>programmed and so we should only match 'nvidia,tegra194-smmu'. In fact, I think that we also need to update the arm_smmu_of_match table to add 'nvidia,tegra194-smmu' with the data set to &arm_mmu500. >>> >>> In that case, new binding "nvidia,smmu-v2" can be added with data set to &arm_mmu500 and enumeration would have nvidia,tegra194-smmu and another variant for next generation SoC in future. > >> I think you would be better off with nvidia,smmu-500 as smmu-v2 appears to be something different. I see others have a smmu-v2 but I am not sure if that is legacy. We have an smmu-500 and so that would seem more appropriate. > > I tried to use the binding synonymous to other vendors. > V2 is the architecture version. MMU-500 is the actual implementation from ARM based on V2 arch. As we just use the MMU-500 IP as it is, It can be named as nvidia,smmu-500 or similar as well. Yup, that sounds OK to me if you want a broader compatible to potentially match other future SoCs as well. > Others probably having their own implementation based on V2 arch. Exactly - "cavium,smmu-v2" and "qcom,smmu-v2" are their own in-house microarchitectures, not one of Arm's designs, so they don't really have a suitable 'product name' we could have used for the bindings. Robin. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 186E8C433E0 for ; Thu, 2 Jul 2020 16:05:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F15B420656 for ; Thu, 2 Jul 2020 16:05:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726365AbgGBQFT (ORCPT ); Thu, 2 Jul 2020 12:05:19 -0400 Received: from foss.arm.com ([217.140.110.172]:38940 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725915AbgGBQFS (ORCPT ); Thu, 2 Jul 2020 12:05:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DD53C1FB; Thu, 2 Jul 2020 09:05:17 -0700 (PDT) Received: from [10.57.21.32] (unknown [10.57.21.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D70973F71E; Thu, 2 Jul 2020 09:05:14 -0700 (PDT) Subject: Re: [PATCH v8 2/3] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU To: Krishna Reddy , Jonathan Hunter Cc: "joro@8bytes.org" , "will@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux-foundation.org" , "linux-kernel@vger.kernel.org" , "linux-tegra@vger.kernel.org" , Thierry Reding , Yu-Huan Hsu , Sachin Nikam , Pritesh Raithatha , Timo Alho , Bitan Biswas , Mikko Perttunen , Nicolin Chen , Bryan Huntsman , "nicoleotsuka@gmail.com" References: <20200630001051.12350-1-vdumpa@nvidia.com> <20200630001051.12350-3-vdumpa@nvidia.com> <3e655881-bac4-f083-44ed-cfa0a61298d0@arm.com> <0d4f46d6-6a4e-bca0-bcf3-0e22a950e57b@nvidia.com> From: Robin Murphy Message-ID: <04e35d51-5e65-047d-90ef-a2de901eb15d@arm.com> Date: Thu, 2 Jul 2020 17:05:05 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2020-07-01 20:39, Krishna Reddy wrote: > On 01/07/2020 20:00, Krishna Reddy wrote: >>>>>>> + items: >>>>>>> + - enum: >>>>>>> + - nvdia,tegra194-smmu >>>>>>> + - const: arm,mmu-500 >>>>> >>>>>> Is the fallback compatible appropriate here? If software treats this as a standard MMU-500 it will only program the first instance (because the second isn't presented as a separate MMU-500) - is there any way that isn't going to blow up? >>>>> >>>>> When compatible is set to both nvidia,tegra194-smmu and arm,mmu-500, implementation override ensure that both instances are programmed. Isn't it? I am not sure I follow your comment fully. >>> >>>> The problem is, if for some reason someone had a Tegra194, but only set the compatible string to 'arm,mmu-500' it would assume that it was a normal arm,mmu-500 and only one instance would be programmed. We always want at least 2 of the 3 instances >>programmed and so we should only match 'nvidia,tegra194-smmu'. In fact, I think that we also need to update the arm_smmu_of_match table to add 'nvidia,tegra194-smmu' with the data set to &arm_mmu500. >>> >>> In that case, new binding "nvidia,smmu-v2" can be added with data set to &arm_mmu500 and enumeration would have nvidia,tegra194-smmu and another variant for next generation SoC in future. > >> I think you would be better off with nvidia,smmu-500 as smmu-v2 appears to be something different. I see others have a smmu-v2 but I am not sure if that is legacy. We have an smmu-500 and so that would seem more appropriate. > > I tried to use the binding synonymous to other vendors. > V2 is the architecture version. MMU-500 is the actual implementation from ARM based on V2 arch. As we just use the MMU-500 IP as it is, It can be named as nvidia,smmu-500 or similar as well. Yup, that sounds OK to me if you want a broader compatible to potentially match other future SoCs as well. > Others probably having their own implementation based on V2 arch. Exactly - "cavium,smmu-v2" and "qcom,smmu-v2" are their own in-house microarchitectures, not one of Arm's designs, so they don't really have a suitable 'product name' we could have used for the bindings. Robin.