diff for duplicates of <04f7bd2a7d69ab7d02c88cf05bda5ae0c4cb6573.camel@mediatek.com> diff --git a/N1/2.bin b/N1/2.bin new file mode 100644 index 0000000..875c889 --- /dev/null +++ b/N1/2.bin @@ -0,0 +1,160 @@ +<html><body><p> +<pre> +Hi Krzysztof, + +Thanks for the reviews. + +On Wed, 2024-12-11 at 10:37 +0100, Krzysztof Kozlowski wrote: +> External email : Please do not click links or open attachments until +> you have verified the sender or the content. +>  +>  +> On Wed, Dec 11, 2024 at 11:22:49AM +0800, Jason-JH.Lin wrote: +> > Add the Global Command Engine (GCE) header file to define the GCE +> > thread priority, GCE subsys ID and GCE events for MT8196. +>  +> This we see from the diff. What we do not see is why priority is a +> binding. Looking briefly at existing code: it is not a binding, there +> is +> no driver user. +>  + +This priority value is used to configure the priority level for each +GCE hardware thread, so it is a necessary hardware attribute. + +It's hard to find where the priority is used in existing driver code +because we parsed it from DTS. + +It is used in all mediaTeks' DTS using the GCE. +For example, in mt8195.dts: + +vdosys0: syscon@1c01a000 { +    compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", +"syscon"; +    reg = <0 0x1c01a000 0 0x1000>; +    mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; +    #clock-cells = <1>; +    mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; +} + +CMDQ driver(mtk-cmdq-mailbox.c) will get the args parsed from mboxes +property in cmdq_xlate() and then it will store CMDQ_THR_PRIO_4 to the +specific thread structure.  +The user of CMDQ driver will send command to CMDQ driver by  +cmdq_mbox_send_data(), and this priority setting will be configured to +GCE hardware thread. + +> >  +> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> +> > --- +> >  .../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1439 +> > +++++++++++++++++ +> >  1 file changed, 1439 insertions(+) +> >  create mode 100644 include/dt-bindings/mailbox/mediatek,mt8196- +> > gce.h +> >  +> > diff --git a/include/dt-bindings/mailbox/mediatek,mt8196-gce.h +> > b/include/dt-bindings/mailbox/mediatek,mt8196-gce.h +> > new file mode 100644 +> > index 000000000000..860d69100157 +> > --- /dev/null +> > +++ b/include/dt-bindings/mailbox/mediatek,mt8196-gce.h +> > @@ -0,0 +1,1439 @@ +> > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +> > +/* +> > + * Copyright (c) 2024 MediaTek Inc. +> > + * +> > + */ +> > + +> > +#ifndef _DT_BINDINGS_GCE_MT8196_H +> > +#define _DT_BINDINGS_GCE_MT8196_H +> > + +> > +/* GCE thread priority */ +> > +#define CMDQ_THR_PRIO_LOWEST 0 +> > +#define CMDQ_THR_PRIO_1              1 +> > +#define CMDQ_THR_PRIO_2              2 +> > +#define CMDQ_THR_PRIO_3              3 +> > +#define CMDQ_THR_PRIO_4              4 +> > +#define CMDQ_THR_PRIO_5              5 +> > +#define CMDQ_THR_PRIO_6              6 +> > +#define CMDQ_THR_PRIO_HIGHEST        7 +> > + +> > +/* GCE subsys table */ +> > +#define SUBSYS_1300XXXX              0 +> > +#define SUBSYS_1400XXXX              1 +> > +#define SUBSYS_1401XXXX              2 +> > +#define SUBSYS_1402XXXX              3 +> > +#define SUBSYS_1502XXXX              4 +> > +#define SUBSYS_1880XXXX              5 +> > +#define SUBSYS_1881XXXX              6 +> > +#define SUBSYS_1882XXXX              7 +> > +#define SUBSYS_1883XXXX              8 +> > +#define SUBSYS_1884XXXX              9 +> > +#define SUBSYS_1000XXXX              10 +> > +#define SUBSYS_1001XXXX              11 +> > +#define SUBSYS_1002XXXX              12 +> > +#define SUBSYS_1003XXXX              13 +> > +#define SUBSYS_1004XXXX              14 +> > +#define SUBSYS_1005XXXX              15 +> > +#define SUBSYS_1020XXXX              16 +> > +#define SUBSYS_1028XXXX              17 +> > +#define SUBSYS_1700XXXX              18 +> > +#define SUBSYS_1701XXXX              19 +> > +#define SUBSYS_1702XXXX              20 +> > +#define SUBSYS_1703XXXX              21 +> > +#define SUBSYS_1800XXXX              22 +> > +#define SUBSYS_1801XXXX              23 +> > +#define SUBSYS_1802XXXX              24 +> > +#define SUBSYS_1804XXXX              25 +> > +#define SUBSYS_1805XXXX              26 +> > +#define SUBSYS_1808XXXX              27 +> > +#define SUBSYS_180aXXXX              28 +> > +#define SUBSYS_180bXXXX              29 +> > +#define SUBSYS_NO_SUPPORT    99 +> > + +> > +/* +> > + * GCE General Purpose Register (GPR) support +> > + * Leave note for scenario usage here +> > + */ +> > +/* GCE: write mask */ +>  +> That's a definite no-go. Register masks are not bindings. +>  + +I'm sorry to the confusion. + +These defines are the index of GCE General Purpose Register for +generating instructions, they are not register masks. + +The comment "/* GCE: write mask */" is briefly describe that the usage +of GCE_GPR_R0 and GCE_GPR_R01 is used to store the register mask when +GCE executing the WRITE instruction. And it can also store the register +mask of POLL and READ instruction. + +I will add more words to make this comment clearer, like this: +/*GCE: store the mask of instruction */ + +Regards, +Jason-JH.Lin + +> > +#define GCE_GPR_R00          0x0 +> > +#define GCE_GPR_R01          0x1 +>  +> Best regards, +> Krzysztof +>  + +</pre> +</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ******************** +The information contained in this e-mail message (including any +attachments) may be confidential, proprietary, privileged, or otherwise +exempt from disclosure under applicable laws. It is intended to be +conveyed only to the designated recipient(s). Any use, dissemination, +distribution, printing, retaining or copying of this e-mail (including its +attachments) by unintended recipient(s) is strictly prohibited and may +be unlawful. If you are not an intended recipient of this e-mail, or believe +that you have received this e-mail in error, please notify the sender +immediately (by replying to this e-mail), delete any and all copies of +this e-mail (including any attachments) from your system, and do not +disclose the content of this e-mail to any other person. Thank you! +</pre><!--}--> diff --git a/N1/2.hdr b/N1/2.hdr new file mode 100644 index 0000000..da1f671 --- /dev/null +++ b/N1/2.hdr @@ -0,0 +1,3 @@ +Content-Type: text/html; + charset="utf-8" +Content-Transfer-Encoding: base64 diff --git a/a/content_digest b/N1/content_digest index 4d8f4f8..c6e1da6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -26,7 +26,7 @@ jassisinghbrar@gmail.com <jassisinghbrar@gmail.com> krzk+dt@kernel.org <krzk+dt@kernel.org> " AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>\0" - "\00:1\0" + "\01:1\0" "b\0" "Hi Krzysztof,\n" "\n" @@ -171,5 +171,167 @@ "> Best regards,\n" "> Krzysztof\n" > + "\01:2\0" + "b\0" + "<html><body><p>\r\n" + "<pre>\r\n" + "Hi Krzysztof,\r\n" + "\r\n" + "Thanks for the reviews.\r\n" + "\r\n" + "On Wed, 2024-12-11 at 10:37 +0100, Krzysztof Kozlowski wrote:\r\n" + "> External email : Please do not click links or open attachments until\r\n" + "> you have verified the sender or the content.\r\n" + "> \r\n" + "> \r\n" + "> On Wed, Dec 11, 2024 at 11:22:49AM +0800, Jason-JH.Lin wrote:\r\n" + "> > Add the Global Command Engine (GCE) header file to define the GCE\r\n" + "> > thread priority, GCE subsys ID and GCE events for MT8196.\r\n" + "> \r\n" + "> This we see from the diff. What we do not see is why priority is a\r\n" + "> binding. Looking briefly at existing code: it is not a binding, there\r\n" + "> is\r\n" + "> no driver user.\r\n" + "> \r\n" + "\r\n" + "This priority value is used to configure the priority level for each\r\n" + "GCE hardware thread, so it is a necessary hardware attribute.\r\n" + "\r\n" + "It's hard to find where the priority is used in existing driver code\r\n" + "because we parsed it from DTS.\r\n" + "\r\n" + "It is used in all mediaTeks' DTS using the GCE.\r\n" + "For example, in mt8195.dts:\r\n" + "\r\n" + "vdosys0: syscon@1c01a000 {\r\n" + "    compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys",\r\n" + ""syscon";\r\n" + "    reg = <0 0x1c01a000 0 0x1000>;\r\n" + "    mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;\r\n" + "    #clock-cells = <1>;\r\n" + "    mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;\r\n" + "}\r\n" + "\r\n" + "CMDQ driver(mtk-cmdq-mailbox.c) will get the args parsed from mboxes\r\n" + "property in cmdq_xlate() and then it will store CMDQ_THR_PRIO_4 to the\r\n" + "specific thread structure. \r\n" + "The user of CMDQ driver will send command to CMDQ driver by \r\n" + "cmdq_mbox_send_data(), and this priority setting will be configured to\r\n" + "GCE hardware thread.\r\n" + "\r\n" + "> > \r\n" + "> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>\r\n" + "> > ---\r\n" + "> >  .../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1439\r\n" + "> > +++++++++++++++++\r\n" + "> >  1 file changed, 1439 insertions(+)\r\n" + "> >  create mode 100644 include/dt-bindings/mailbox/mediatek,mt8196-\r\n" + "> > gce.h\r\n" + "> > \r\n" + "> > diff --git a/include/dt-bindings/mailbox/mediatek,mt8196-gce.h\r\n" + "> > b/include/dt-bindings/mailbox/mediatek,mt8196-gce.h\r\n" + "> > new file mode 100644\r\n" + "> > index 000000000000..860d69100157\r\n" + "> > --- /dev/null\r\n" + "> > +++ b/include/dt-bindings/mailbox/mediatek,mt8196-gce.h\r\n" + "> > @@ -0,0 +1,1439 @@\r\n" + "> > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */\r\n" + "> > +/*\r\n" + "> > + * Copyright (c) 2024 MediaTek Inc.\r\n" + "> > + *\r\n" + "> > + */\r\n" + "> > +\r\n" + "> > +#ifndef _DT_BINDINGS_GCE_MT8196_H\r\n" + "> > +#define _DT_BINDINGS_GCE_MT8196_H\r\n" + "> > +\r\n" + "> > +/* GCE thread priority */\r\n" + "> > +#define CMDQ_THR_PRIO_LOWEST 0\r\n" + "> > +#define CMDQ_THR_PRIO_1              1\r\n" + "> > +#define CMDQ_THR_PRIO_2              2\r\n" + "> > +#define CMDQ_THR_PRIO_3              3\r\n" + "> > +#define CMDQ_THR_PRIO_4              4\r\n" + "> > +#define CMDQ_THR_PRIO_5              5\r\n" + "> > +#define CMDQ_THR_PRIO_6              6\r\n" + "> > +#define CMDQ_THR_PRIO_HIGHEST        7\r\n" + "> > +\r\n" + "> > +/* GCE subsys table */\r\n" + "> > +#define SUBSYS_1300XXXX              0\r\n" + "> > +#define SUBSYS_1400XXXX              1\r\n" + "> > +#define SUBSYS_1401XXXX              2\r\n" + "> > +#define SUBSYS_1402XXXX              3\r\n" + "> > +#define SUBSYS_1502XXXX              4\r\n" + "> > +#define SUBSYS_1880XXXX              5\r\n" + "> > +#define SUBSYS_1881XXXX              6\r\n" + "> > +#define SUBSYS_1882XXXX              7\r\n" + "> > +#define SUBSYS_1883XXXX              8\r\n" + "> > +#define SUBSYS_1884XXXX              9\r\n" + "> > +#define SUBSYS_1000XXXX              10\r\n" + "> > +#define SUBSYS_1001XXXX              11\r\n" + "> > +#define SUBSYS_1002XXXX              12\r\n" + "> > +#define SUBSYS_1003XXXX              13\r\n" + "> > +#define SUBSYS_1004XXXX              14\r\n" + "> > +#define SUBSYS_1005XXXX              15\r\n" + "> > +#define SUBSYS_1020XXXX              16\r\n" + "> > +#define SUBSYS_1028XXXX              17\r\n" + "> > +#define SUBSYS_1700XXXX              18\r\n" + "> > +#define SUBSYS_1701XXXX              19\r\n" + "> > +#define SUBSYS_1702XXXX              20\r\n" + "> > +#define SUBSYS_1703XXXX              21\r\n" + "> > +#define SUBSYS_1800XXXX              22\r\n" + "> > +#define SUBSYS_1801XXXX              23\r\n" + "> > +#define SUBSYS_1802XXXX              24\r\n" + "> > +#define SUBSYS_1804XXXX              25\r\n" + "> > +#define SUBSYS_1805XXXX              26\r\n" + "> > +#define SUBSYS_1808XXXX              27\r\n" + "> > +#define SUBSYS_180aXXXX              28\r\n" + "> > +#define SUBSYS_180bXXXX              29\r\n" + "> > +#define SUBSYS_NO_SUPPORT    99\r\n" + "> > +\r\n" + "> > +/*\r\n" + "> > + * GCE General Purpose Register (GPR) support\r\n" + "> > + * Leave note for scenario usage here\r\n" + "> > + */\r\n" + "> > +/* GCE: write mask */\r\n" + "> \r\n" + "> That's a definite no-go. Register masks are not bindings.\r\n" + "> \r\n" + "\r\n" + "I'm sorry to the confusion.\r\n" + "\r\n" + "These defines are the index of GCE General Purpose Register for\r\n" + "generating instructions, they are not register masks.\r\n" + "\r\n" + "The comment "/* GCE: write mask */" is briefly describe that the usage\r\n" + "of GCE_GPR_R0 and GCE_GPR_R01 is used to store the register mask when\r\n" + "GCE executing the WRITE instruction. And it can also store the register\r\n" + "mask of POLL and READ instruction.\r\n" + "\r\n" + "I will add more words to make this comment clearer, like this:\r\n" + "/*GCE: store the mask of instruction */\r\n" + "\r\n" + "Regards,\r\n" + "Jason-JH.Lin\r\n" + "\r\n" + "> > +#define GCE_GPR_R00          0x0\r\n" + "> > +#define GCE_GPR_R01          0x1\r\n" + "> \r\n" + "> Best regards,\r\n" + "> Krzysztof\r\n" + "> \r\n" + "\r\n" + "</pre>\r\n" + "</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ********************\r\n" + "The information contained in this e-mail message (including any \r\n" + "attachments) may be confidential, proprietary, privileged, or otherwise\r\n" + "exempt from disclosure under applicable laws. It is intended to be \r\n" + "conveyed only to the designated recipient(s). Any use, dissemination, \r\n" + "distribution, printing, retaining or copying of this e-mail (including its \r\n" + "attachments) by unintended recipient(s) is strictly prohibited and may \r\n" + "be unlawful. If you are not an intended recipient of this e-mail, or believe \r\n" + "that you have received this e-mail in error, please notify the sender \r\n" + "immediately (by replying to this e-mail), delete any and all copies of \r\n" + "this e-mail (including any attachments) from your system, and do not\r\n" + "disclose the content of this e-mail to any other person. Thank you!\r\n" + </pre><!--}--> -80cd5c11069946eb3bc57d96fce55324270abad198fbe00df34646f736ad56a6 +a1182b220af439c0ee50f8f984894d288fa6e1798dd5b68495abd3f64a023d04
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.