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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN2PEPF000044A1.mail.protection.outlook.com (10.167.243.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.159.10 via Frontend Transport; Mon, 22 Jun 2026 10:03:45 +0000 Received: from [10.128.114.94] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 22 Jun 2026 05:03:34 -0500 Message-ID: <054690e9-9113-49a6-844b-79d85045a3db@amd.com> Date: Mon, 22 Jun 2026 15:33:31 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/7] drivers/migrate_offload: add DMA batch copy driver (dcbm) To: Karim Manaouil CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20260428155043.39251-2-shivankg@amd.com> <20260428155043.39251-14-shivankg@amd.com> <20260619160725.lfcxrbj5go67qy6u@wrangler> Content-Language: en-US From: "Garg, Shivank" In-Reply-To: <20260619160725.lfcxrbj5go67qy6u@wrangler> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 89BC22yfbQ4cp/TOlts4raiKo6M8y46/ruT1cbIyozAL+J3OTlPXRu6C8nTCM6hbwOLkl2SghWo5RYDHxWeh1mygnH6iEDHm2TtB7XEvgqBg5kpCVy5nFl3cqvZeMm0RtT5a0XFIepyJXucggrwpHyHkOZYTkaMgHRfBR+8cZqAiJeudh91GzJFUVvOqC2rAxMyUrWCfPxaixogcb85YoyvecAXed83Ijl6611Hkfra8s2qR9/UzclXgqk0+rVDgxWOm1Pim5DaJasCXs+fRFgSiVrkN0Jak99ST8CreJsBFhy8zMMgEtj2UP5pAmJ9PjQkil6fBrqx7titDmpsQvfdtH/QKSdQ1EaS3OGtjyOPgX716ixivXHcIB+9Xq3quyskn7FTSp7Y1pAEp02EpYDdCtQy022/iEsG28GkC+axDLfiobx7v4vsaXVwtklaO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2026 10:03:45.7850 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7e435ef-f0ca-49d6-9c8e-08ded0458c4b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7223 On 6/19/2026 9:37 PM, Karim Manaouil wrote: > [You don't often get email from kmanaouil.dev@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > Hi again Shivank, > > I just got some time to resume testing this on Intel Sapphire Rapids and > something caught my attention, below > > On Tue, Apr 28, 2026 at 03:50:49PM +0000, Shivank Garg wrote: >> +static int submit_dma_transfers(struct dma_work *work) >> +{ >> + struct scatterlist *sg_src, *sg_dst; >> + struct dma_async_tx_descriptor *tx; >> + unsigned long flags = DMA_CTRL_ACK; >> + dma_cookie_t cookie; >> + int i; >> + >> + atomic_set(&work->pending, 1); >> + >> + sg_src = work->src_sgt->sgl; >> + sg_dst = work->dst_sgt->sgl; >> + for_each_sgtable_dma_sg(work->src_sgt, sg_src, i) { >> + if (i == work->src_sgt->nents - 1) >> + flags |= DMA_PREP_INTERRUPT; >> + >> + tx = dmaengine_prep_dma_memcpy(work->chan, >> + sg_dma_address(sg_dst), >> + sg_dma_address(sg_src), >> + sg_dma_len(sg_src), flags); >> + if (!tx) { >> + atomic_set(&work->pending, 0); >> + return -EIO; >> + } >> + >> + if (i == work->src_sgt->nents - 1) { >> + tx->callback = dma_completion_callback; >> + tx->callback_param = work; >> + } >> + > > Here, you are submitting the descriptors one after the other and only > the last descriptor has a callback, which in theory sounds correct as > you expect the DMA engine to complete the descriptors in the same order > they were submitted. However, in reality that's not really gauranteed. > > Intel DSA in particular can complete descriptors out of order. That > means, the last descriptor submitted may not necessarily be the last > descriptors that completes. In that case, you will return in > folios_copy_dma() before the copy truly completes for all the folios. > > For correctness, we have to add a callback to every descriptor and > initialize work->pending to the number of descriptors submitted then > every time a descriptor completes, you call atomic_dec(&work->pending) > and only complete the completion the moment it reaches zero. > > Btw, waiting for an interrupt adds massive scheduling overhead. If we > also add the logic above, it'll get even worse. In my measurements, this > can easily add up to 6ms, by which CPU page copy have easily completed > the entire copy, which again adds to the list of latency concerns I > raised in my other reply. Thanks Karim for catching this. I was not aware that descriptor chaining was not applicable for DSA. Going forward, implementing the device_prep_dma_memcpy_sg() fixes this broken assumption. So client will issue single transaction and see single completion for whole batch. The ordering/correctness will become provider's responsibility. Thanks, Shivank