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Thu, 30 Oct 2025 00:07:25 -0700 (PDT) Message-ID: <06207703-caaa-4e81-b218-838609e3cc52@suse.com> Date: Thu, 30 Oct 2025 08:07:23 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH for-4.22 1/2] x86/platform: Expose DTS sensors MSR To: Andrew Cooper Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org, Teddy Astie References: <48b15617f248852560a0e0674eea65d25330c605.1761585640.git.teddy.astie@vates.tech> <83712d12-08ec-46a4-b215-18f7ea1c1069@citrix.com> <78fe46d2-f21a-46d2-bcb5-a54d7cd86e91@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 29.10.2025 17:06, Andrew Cooper wrote: > On 28/10/2025 9:20 am, Jan Beulich wrote: >> On 27.10.2025 20:38, Andrew Cooper wrote: >>> On 27/10/2025 5:26 pm, Teddy Astie wrote: >>>> I'm not a fan of doing a inline cpuid check here, but I don't have a >>>> better approach in mind. >>> I'm not sure if there's enough information in leaf 6 to justify putting >>> it fully into the CPUID infrastructure. >>> >>> But, if you do something like this: >>> >>> diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86/cpu-policy.h >>> index f94f23e159d2..d02fe4d22151 100644 >>> --- a/xen/include/xen/lib/x86/cpu-policy.h >>> +++ b/xen/include/xen/lib/x86/cpu-policy.h >>> @@ -121,7 +121,13 @@ struct cpu_policy >>>              uint64_t :64, :64; /* Leaf 0x3 - PSN. */ >>>              uint64_t :64, :64; /* Leaf 0x4 - Structured Cache. */ >>>              uint64_t :64, :64; /* Leaf 0x5 - MONITOR. */ >>> -            uint64_t :64, :64; /* Leaf 0x6 - Therm/Perf. */ >>> + >>> +            /* Leaf 0x6 - Thermal and Perf. */ >>> +            struct { >>> +                bool /* a */ dts:1; >>> +                uint32_t /* b */:32, /* c */:32, /* d */:32; >>> +            }; >>> + >>>              uint64_t :64, :64; /* Leaf 0x7 - Structured Features. */ >>>              uint64_t :64, :64; /* Leaf 0x8 - rsvd */ >>>              uint64_t :64, :64; /* Leaf 0x9 - DCA */ >> Just to mention, below a patch I have pending as part of a series to >> e.g. replace the various CPUID6_* values we presently use. As you did >> indicate when we talked about this, a prereq to then use respective >> bits from host_policy is an adjustment to cpu-policy.c, which is also >> part of that series. If we weren't in freeze right now, I would have >> posted the series already. >> >> Jan >> >> x86/cpu-policy: define bits of leaf 6 >> >> ... as far as we presently use them in the codebase. >> >> Signed-off-by: Jan Beulich >> --- >> Or should we make both parts proper featureset elements? At least >> APERFMPERF could likely be made visible to guests (in principle). >> >> --- a/xen/include/xen/lib/x86/cpu-policy.h >> +++ b/xen/include/xen/lib/x86/cpu-policy.h >> @@ -128,7 +128,31 @@ struct cpu_policy >> uint64_t :64, :64; /* Leaf 0x3 - PSN. */ >> uint64_t :64, :64; /* Leaf 0x4 - Structured Cache. */ >> uint64_t :64, :64; /* Leaf 0x5 - MONITOR. */ >> - uint64_t :64, :64; /* Leaf 0x6 - Therm/Perf. */ >> + >> + /* Leaf 0x6 - Therm/Perf. */ >> + struct { >> + uint32_t /* a */:1, >> + turbo:1, >> + arat:1, >> + :4, >> + hwp:1, >> + hwp_notification:1, >> + hwp_activity_window:1, >> + hwp_epp:1, >> + hwp_plr:1, >> + :1, >> + hdc:1, >> + :2, >> + hwp_peci:1, >> + :2, >> + hw_feedback:1, >> + :12; >> + uint32_t /* b */:32; >> + uint32_t /* c */ aperfmperf:1, >> + :31; >> + uint32_t /* d */:32; >> + } pm; > > This works too, although we don't have 'pm' equivalents elsewhere in > this part of the union. > > APERF/MPERF is a disaster of an interface.  It can't safely be read even > in root mode, because an NMI/SMI breaks the algorithm in a way that > isn't easy to spot and retry.  On AMD, it's marginally better because > GIF can be used to exclude NMIs and non-fatal MCEs while sampling the > register pair. > > In a VM, it's simply unusable.  Any VMExit, and even a vCPU reschedule, > breaks reading the pair. > > Until the CPU vendors produce a way of reading the two counters together > (i.e. atomically, which has been asked for, repeatedly), there's no > point considering it for use in a VM. Right now none of this is meant for exposure. It's solely for us to use the bits in the host policy. Jan