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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7065119f2bfsm30612b3a.81.2024.06.20.12.53.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Jun 2024 12:53:37 -0700 (PDT) Message-ID: <06793da0-e0ad-4dfd-a3ca-9242463e37b2@ventanamicro.com> Date: Thu, 20 Jun 2024 16:53:32 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] target/riscv: Add standard extension implied rules To: frank.chang@sifive.com, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" , Jerry Zhang Jian , Max Chou References: <20240616024657.17948-1-frank.chang@sifive.com> <20240616024657.17948-5-frank.chang@sifive.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20240616024657.17948-5-frank.chang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 6/15/24 11:46 PM, frank.chang@sifive.com wrote: > From: Frank Chang > > Add standard extension implied rules to enable the implied extensions of > the standard extension recursively. > > Signed-off-by: Frank Chang > Reviewed-by: Jerry Zhang Jian > Tested-by: Max Chou > Acked-by: Alistair Francis > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu.c | 340 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 340 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d09b5e9e62..1a3b1387e1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2297,12 +2297,352 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = { > }, > }; > > +static RISCVCPUImpliedExtsRule ZCB_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zcb), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zca), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZCD_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zcd), > + .implied_misas = RVD, > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zca), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZCE_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zce), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp), > + CPU_CFG_OFFSET(ext_zcmt), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZCF_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zcf), > + .implied_misas = RVF, > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zca), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZCMP_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zcmp), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zca), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZCMT_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zcmt), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZDINX_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zdinx), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zfinx), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZFA_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zfa), > + .implied_misas = RVF, > + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END }, > +}; > + > +static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zfbfmin), > + .implied_misas = RVF, > + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END }, > +}; > + > +static RISCVCPUImpliedExtsRule ZFH_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zfh), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zfhmin), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zfhmin), > + .implied_misas = RVF, > + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END }, > +}; > + > +static RISCVCPUImpliedExtsRule ZFINX_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zfinx), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zicsr), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZHINX_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zhinx), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zhinxmin), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zhinxmin), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zfinx), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zicntr), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zicsr), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zihpm), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zicsr), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZK_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zk), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr), > + CPU_CFG_OFFSET(ext_zkt), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZKN_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zkn), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc), > + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne), > + CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZKS_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zks), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc), > + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed), > + CPU_CFG_OFFSET(ext_zksh), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVBB_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvbb), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvkb), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zve32f), > + .implied_misas = RVF, > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zve32x), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zve32x), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zicsr), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zve64d), > + .implied_misas = RVD, > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zve64f), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zve64f), > + .implied_misas = RVF, > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zve64x), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zve32x), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvfbfmin), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zve32f), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvfbfwma), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVFH_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvfh), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvfhmin), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zve32f), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvkn), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb), > + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvknc), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvkng), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvknhb), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zve64x), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVKS_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvks), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh), > + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvksc), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_zvksg), > + .implied_exts = { > + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = { > &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, > &RVM_IMPLIED, &RVV_IMPLIED, NULL > }; > > RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = { > + &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED, > + &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED, > + &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED, > + &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED, > + &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED, > + &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED, > + &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, > + &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, > + &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, > + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, > + &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, > + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, > NULL > }; >