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Tue, 11 Nov 2025 06:52:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IHPNkW8hxtm48MCmWzwGS5Xaut0loCR++uqJQRZWgnCErEm9erUxXbzVLKElqgpRN181cAIlQ== X-Received: by 2002:a17:90b:4c8a:b0:340:fb6a:cb4c with SMTP id 98e67ed59e1d1-3436cd064efmr16227916a91.30.1762872728121; Tue, 11 Nov 2025 06:52:08 -0800 (PST) Received: from [10.206.103.12] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-343d0173239sm1432594a91.16.2025.11.11.06.52.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Nov 2025 06:52:07 -0800 (PST) Message-ID: <07221941-4546-4153-b845-594be006e79a@oss.qualcomm.com> Date: Tue, 11 Nov 2025 20:21:59 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] dt-bindings: display/msm/rgmu: Document A612 RGMU To: Krzysztof Kozlowski Cc: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Jessica Zhang , Dan Carpenter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang References: <20251107-qcs615-spin-2-v2-0-a2d7c4fbf6e6@oss.qualcomm.com> <20251107-qcs615-spin-2-v2-3-a2d7c4fbf6e6@oss.qualcomm.com> <20251110-persimmon-wombat-of-holiness-6b3f9c@kuoka> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <20251110-persimmon-wombat-of-holiness-6b3f9c@kuoka> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Pc3yRyhd c=1 sm=1 tr=0 ts=69134d99 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=UXIAUNObAAAA:8 a=EUspDBNiAAAA:8 a=9x9RmpQyoqOX9MKIOEcA:9 a=QEXdDO2ut3YA:10 a=bFq2RbqkfqsA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=sptkURWiP4Gy88Gu7hUp:22 a=a1s67YnXd6TbAZZNj1wK:22 a=poXaRoVlC6wW9_mwW8W4:22 X-Proofpoint-ORIG-GUID: i3l7fGyosF2ISYx5E3VKcN2wVqCVjh9l X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTExMDEyMCBTYWx0ZWRfX72XnhNMBCVxk rJryDDESs7HZB5yGw2LdWQVTJYIeltlL4f0UuRMBYYbjttr0hLOIg3NkIJCh2FOCnnPVX/jSZNH +HP8niHbpDWRk9WfROmN4Xm3EawAKqO8WrRHBEGOerb05JTN0SDUFpcPr6TPbal41pSsSgLyht5 hO1imMA9lYoqXEgJ+OGy1iZd+N4rpkTc+1AsHVroyBM6iT4Outp2g1ZnrtAjsKigPFQKSMUiBsk U5mbAJOnBkObYemrLrkTw6YCxNuiH6OBVFty/Ivcj03tI7u3+7znVNbq7sZTlQ1PHT8w186m3z6 g0tZvhgiIj7wfHcGfEVZOHoMxjkcsnz9LIbHxUE+tgvpXwZKfz/1bynhLrSCAG/UaZoLn8JSUWp +ExFJK5ArNo92XKj8bG4a892opLu6Q== X-Proofpoint-GUID: i3l7fGyosF2ISYx5E3VKcN2wVqCVjh9l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-11_02,2025-11-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511110120 On 11/10/2025 1:21 PM, Krzysztof Kozlowski wrote: > On Fri, Nov 07, 2025 at 02:20:08AM +0530, Akhil P Oommen wrote: >> From: Jie Zhang >> >> RGMU a.k.a Reduced Graphics Management Unit is a small state machine >> with the sole purpose of providing IFPC (Inter Frame Power Collapse) >> support. Compared to GMU, it doesn't manage GPU clock, voltage >> scaling, bw voting or any other functionalities. All it does is detect >> an idle GPU and toggle the GDSC switch. As it doesn't access DDR space, >> it doesn't require iommu. >> >> So far, only Adreno 612 GPU has an RGMU core. Document RGMU in the GMU's >> schema. >> >> Signed-off-by: Jie Zhang >> Signed-off-by: Akhil P Oommen >> --- >> .../devicetree/bindings/display/msm/rgmu.yaml | 131 +++++++++++++++++++++ >> MAINTAINERS | 1 + >> 2 files changed, 132 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/display/msm/rgmu.yaml b/Documentation/devicetree/bindings/display/msm/rgmu.yaml >> new file mode 100644 >> index 000000000000..7621556477d0 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/msm/rgmu.yaml > > Filename matching compatible, so qcom,adreno-rgmu.yaml > > >> @@ -0,0 +1,131 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >> +%YAML 1.2 >> +--- >> + >> +$id: http://devicetree.org/schemas/display/msm/rgmu.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: RGMU attached to certain Adreno GPUs >> + >> +maintainers: >> + - Rob Clark >> + >> +description: | > > Do not need '|' unless you need to preserve formatting. > >> + RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that >> + belong to Adreno A6xx family. It is a small state machine that helps to >> + toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save >> + power. >> + >> +properties: >> + compatible: >> + items: >> + - const: qcom,adreno-rgmu-612.0 >> + - const: qcom,adreno-rgmu >> + >> + reg: >> + items: >> + - description: Core RGMU registers >> + >> + reg-names: >> + items: >> + - const: gmu > > Drop reg-names, useless for one entry with same name as the block name. > >> + >> + clocks: >> + items: >> + - description: GMU clock >> + - description: GPU CX clock >> + - description: GPU AXI clock >> + - description: GPU MEMNOC clock >> + - description: GPU SMMU vote clock >> + >> + clock-names: >> + items: >> + - const: gmu >> + - const: cxo >> + - const: axi >> + - const: memnoc >> + - const: smmu_vote >> + >> + power-domains: >> + items: >> + - description: CX GDSC power domain >> + - description: GX GDSC power domain >> + >> + power-domain-names: >> + items: >> + - const: cx >> + - const: gx >> + >> + interrupts: >> + items: >> + - description: GMU OOB interrupt >> + - description: GMU interrupt >> + >> + interrupt-names: >> + items: >> + - const: oob >> + - const: gmu >> + >> + operating-points-v2: true >> + opp-table: >> + type: object >> + >> +required: > > compatible > >> + - reg >> + - reg-names >> + - clocks >> + - clock-names >> + - power-domains >> + - power-domain-names >> + - interrupts >> + - interrupt-names > > Keep the same order as in properties. > >> + - operating-points-v2 >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + #include >> + >> + rgmu: rgmu@506a000 { > > Drop label. > > Node names should be generic. See also an explanation and list of > examples (not exhaustive) in DT specification: > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > If you cannot find a name matching your device, please check in kernel > sources for similar cases or you can grow the spec (via pull request to > DT spec repo). I guess we can use 'gmu' here as that name is already in use for other chipsets? Ack for all other suggestions. Will update the patch. -Akhil > > Best regards, > Krzysztof >