From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
To: Animesh Manna <animesh.manna@intel.com>,
<intel-gfx@lists.freedesktop.org>,
<intel-xe@lists.freedesktop.org>
Cc: <uma.shankar@intel.com>, <ville.syrjala@linux.intel.com>,
<jani.nikula@intel.com>
Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
Date: Thu, 21 May 2026 13:48:42 +0530 [thread overview]
Message-ID: <074e4d37-9bf0-45da-9541-8b27164e743c@intel.com> (raw)
In-Reply-To: <20260513163857.1541888-2-animesh.manna@intel.com>
On 13-05-2026 22:08, Animesh Manna wrote:
> CMTG will be enabled only with DC3co, so add a separate function
> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
> DC3co will be enabled in a separate patch.
>
> v2:
> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
>
> v3:
> - Do not access power domain members directly. [Jani]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 15 ++++++++++++++-
> drivers/gpu/drm/i915/display/intel_cmtg.h | 4 ++++
> 2 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..dc039bea452c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -4,7 +4,6 @@
> */
>
> #include <linux/string_choices.h>
> -#include <linux/types.h>
>
> #include <drm/drm_device.h>
> #include <drm/drm_print.h>
> @@ -16,6 +15,7 @@
> #include "intel_display_device.h"
> #include "intel_display_power.h"
> #include "intel_display_regs.h"
> +#include "intel_display_types.h"
>
> /**
> * DOC: Common Primary Timing Generator (CMTG)
> @@ -185,3 +185,16 @@ void intel_cmtg_sanitize(struct intel_display *display)
>
> intel_cmtg_disable(display, &cmtg_config);
> }
> +
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
> + DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> + intel_display_power_get_current_dc_state(display) == DC_STATE_EN_DC3CO)
I would enable CMTG before setting the DC3CO state, since CMTG running is a must condition for DC3CO.
Doing it the current way creates a cyclic dependency.
> + return true;
> +
> + return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..ed540581738f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -6,8 +6,12 @@
> #ifndef __INTEL_CMTG_H__
> #define __INTEL_CMTG_H__
>
> +#include <linux/types.h>
> +
> struct intel_display;
> +struct intel_crtc_state;
>
> void intel_cmtg_sanitize(struct intel_display *display);
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_CMTG_H__ */
next prev parent reply other threads:[~2026-05-21 8:18 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 16:38 [PATCH v6 00/16] CMTG enablement Animesh Manna
2026-05-13 16:38 ` [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-05-21 8:18 ` Dibin Moolakadan Subrahmanian [this message]
2026-05-21 9:01 ` Manna, Animesh
2026-05-21 12:35 ` Dibin Moolakadan Subrahmanian
2026-05-22 5:00 ` Manna, Animesh
2026-05-26 8:26 ` Shankar, Uma
2026-05-13 16:38 ` [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-05-21 8:31 ` Dibin Moolakadan Subrahmanian
2026-05-21 12:11 ` Manna, Animesh
2026-05-21 12:41 ` Dibin Moolakadan Subrahmanian
2026-05-21 17:19 ` Manna, Animesh
2026-05-13 16:38 ` [PATCH v6 03/16] drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info Animesh Manna
2026-05-13 16:38 ` [PATCH v6 04/16] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-05-13 16:38 ` [PATCH v6 05/16] drm/i915/cmtg: Program VRR registers of CMTG Animesh Manna
2026-05-13 16:38 ` [PATCH v6 06/16] drm/i915/cmtg: Set transcoder mn for CMTG Animesh Manna
2026-05-13 16:38 ` [PATCH v6 07/16] drm/i915/cmtg: Add hook to enable CMTG with sync to port Animesh Manna
2026-05-13 16:38 ` [PATCH v6 08/16] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-05-13 16:38 ` [PATCH v6 09/16] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() Animesh Manna
2026-05-13 16:38 ` [PATCH v6 10/16] drm/i915/cmtg: Modify existing hook to disable CMTG Animesh Manna
2026-05-13 16:38 ` [PATCH v6 11/16] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-05-13 16:38 ` [PATCH v6 12/16] drm/i915/cmtg: Add CMTG HWGB programming Animesh Manna
2026-05-13 16:38 ` [PATCH v6 13/16] drm/i915/cmtg: Add CMTG scan line programming Animesh Manna
2026-05-13 16:38 ` [PATCH v6 14/16] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-05-13 16:38 ` [PATCH v6 15/16] drm/i915/cmtg: Restore CMTG after DC6 entry Animesh Manna
2026-05-21 11:46 ` Dibin Moolakadan Subrahmanian
2026-05-22 4:54 ` Manna, Animesh
2026-05-13 16:38 ` [PATCH v6 16/16] [NOT FOR REVIEW] debug patch Animesh Manna
2026-05-13 17:58 ` ✗ CI.checkpatch: warning for CMTG enablement (rev7) Patchwork
2026-05-13 18:00 ` ✓ CI.KUnit: success " Patchwork
2026-05-13 18:56 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-13 20:11 ` ✗ i915.CI.BAT: failure for CMTG enablement (rev6) Patchwork
2026-05-14 17:47 ` ✗ Xe.CI.FULL: failure for CMTG enablement (rev7) Patchwork
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