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Tue, 28 Jul 2026 12:23:38 +0000 (GMT) From: "Alim Akhtar" To: "'Krzysztof Kozlowski'" , "'raghav.s'" , , , , , , , , Cc: , , , , , , , , In-Reply-To: <8582d4f9-1a78-4f47-bab9-c52393dffbd1@kernel.org> Subject: RE: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes Date: Tue, 28 Jul 2026 17:53:37 +0530 Message-ID: <079201dd1e8b$eca22680$c5e67380$@samsung.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIRARWKMB8/axP+0I5R2y9G0OYjygMlHcTpAvLC774CITPxw7XZSnaQ Content-Language: en-us X-CMS-MailID: 20260728122341epcas5p2208334e2a1e6bfd9217cb91d356c505e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260728115256epcas5p38cbcfe68218d08301d237705388e6e62 References: <20260728121111.2077860-1-raghav.s@samsung.com> <20260728121111.2077860-5-raghav.s@samsung.com> <8582d4f9-1a78-4f47-bab9-c52393dffbd1@kernel.org> Hi Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski > Sent: Tuesday, July 28, 2026 5:30 PM > To: raghav.s ; s.nawrocki=40samsung.com; > cw00.choi=40samsung.com; peter.griffin=40linaro.org; > alim.akhtar=40samsung.com; mturquette=40baylibre.com; sboyd=40kernel.org; > bmasney=40redhat.com; robh=40kernel.org; conor+dt=40kernel.org > Cc: linux-samsung-soc=40vger.kernel.org; linux-clk=40vger.kernel.org; > devicetree=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; lin= ux- > kernel=40vger.kernel.org; hajun.sung=40samsung.com; > is.gandhi=40samsung.com; ts.amit=40samsung.com; > pokala.reddy=40samsung.com > Subject: Re: =5BPATCH 04/13=5D arm64: dts: exynos8855: add cmu_top & > cmu_peric clock DT nodes >=20 > On 28/07/2026 14:11, raghav.s wrote: > > Add required dt node for cmu_top & cmu_peric block > > > > Signed-off-by: raghav.s > > --- > > arch/arm64/boot/dts/exynos/exynos8855.dtsi =7C 24 > > ++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) >=20 > Please organize your patches in reasonable order. DTS is never in the mid= dle, > see submitting patches (both documents) and maintainer-soc profile. >=20 The thought was to add clks block wise and hence we see DTS coming in betwe= en but for the other blocks.=20 e.g. patch-2 and 3 adds binding and driver for TOP and PERIC and this patch= -4 adds DTS.=20 And patch-5 and 6 adds binding and driver for PERIS and patch-7 adds DTS an= d so on. Cover-letter should have explained this.=20 Are you suggesting to re-order all the binding first followed by all blocks= driver and then add a single DTS for all clock controller?=20 Does current approach helps in review?=20 > Best regards, > Krzysztof