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This lets each speed mode - and each board via device >>> tree - >>> select an appropriate value. >>> >>> Signed-off-by: Tze Yee Ng >>> --- >> >> The PHY_CTRL default needs to be corrected. All six tables also use the >> same 0x41F0, so this is not actually per-mode. >> >> Please fix the defaults. >> >> Regards, >> Tanmay > > Hi Tanmay, > > 0x41F0 is the PHY_CTRL (0x2080) reset value from the PHY spec. The > driver never wrote this register before, so the PHY already ran at > 0x41F0 in every mode. Using it as the default in all six tables just > preserves that (the write is a no-op unless overridden), while making > the register tunable per mode/board via cdns,phy-ctrl- in DT, > e.g. on Agilex5: > >   013b:    cdns,phy-ctrl-emmc-ddr = <0x4010>; (phony_dqs_timing = 1) >   modular: cdns,phy-ctrl-emmc-ddr = <0x4000>; (phony_dqs_timing = 0) > > > So the defaults match only because the reset value is mode-independent; > the real tuning lives in DT. You're right that six bare 0x41F0 > literals are misleading. For v3 I'll add a named constant > (SDHCI_CDNS6_PHY_CTRL_REG_DEFAULT = 0x000041F0) for the default and > reword the commit to say the register is made programmable with the > reset value as default (no functional change), overridable per > mode/board via DT. > > Does that work for you, or did you expect distinct per-mode defaults? I > don't have validated per-mode values, that tuning is meant to live in DT. > > I expect mode-specific, validated defaults, consistent with the other PHY configuration values in each mode table. Please determine the appropriate default for each speed mode rather than using 0x41F0 universally. Board-specific DT values may still override those defaults where required.