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X-CSE-ConnectionGUID: wyYkD4DuQ5aDuBPWkIf8eg== X-CSE-MsgGUID: VJcaPD2ISgCk7TKgVQFPuw== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="84316028" X-IronPort-AV: E=Sophos;i="6.25,153,1779174000"; d="scan'208";a="84316028" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2026 13:47:33 -0700 X-CSE-ConnectionGUID: W4S9+43UQ0SsgOsyVy4BJA== X-CSE-MsgGUID: 4mAzlO8KRd6FX6clzJ59AA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,153,1779174000"; d="scan'208";a="256308413" Received: from jmaxwel1-mobl.amr.corp.intel.com (HELO [10.125.111.66]) ([10.125.111.66]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2026 13:47:32 -0700 Message-ID: <08c9bf2f-75be-4244-b99c-153ec1f604ca@intel.com> Date: Wed, 8 Jul 2026 13:47:29 -0700 Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 16/17] KVM: TDX: Add in-kernel Quote generation To: Sean Christopherson , Peter Fang Cc: Rick P Edgecombe , "djbw@kernel.org" , "kvm@vger.kernel.org" , "linux-coco@lists.linux.dev" , Xiaoyao Li , "dave.hansen@linux.intel.com" , "baolu.lu@linux.intel.com" , Adrian Hunter , "kas@kernel.org" , "tony.lindgren@linux.intel.com" , Yilun Xu , "linux-kernel@vger.kernel.org" , Sohil Mehta , Zhenzhong Duan , Kishen Maloor , "yilun.xu@linux.intel.com" , "x86@kernel.org" References: <20260618081355.3253581-1-yilun.xu@linux.intel.com> <20260618081355.3253581-17-yilun.xu@linux.intel.com> <20260629100301.GA1743876@pedri> <23a9173f6e278ca7dfedce3374626c6ea3e1b47a.camel@intel.com> <6a445e4be6b12_3a3568100db@djbw-dev.notmuch> <9df36c49e6be69dd9eece71f70a404a84b1563ab.camel@intel.com> <20260704054342.GB2169894@pedri> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 7/6/26 10:57, Sean Christopherson wrote: > What is "the S3M" though? Is it a separate chip a la AMD's PSP/ASP? Is it a > per-package thing? Per-core? I'll give you my rough software guy mental model of what it is: Each package has its own S3M. They are microcontrollers which are discrete from the CPU cores. Each S3M gets some CPU physical address space routed over to it. > How is it accessed, and what are the "rules" for for those > accesses? What types of latencies are we looking at? As far as I know, the latency for one round trip to/from S3M is on the order of a "real" device. It has a physical address and when the OS wants to talk to it, those addresses are mapped with ioremap(). It's similar to any modern I/O device control plane. Note, though, that for TDX, there's no ioremap() because the I/O is hidden in the TDX module. The real overhead comes because the I/O window is essentially 4 bytes wide (IIRC) and all the data that comes in and out of it has to be squeezed through that window. It reminds me of a UART, but with a slightly more arcane interface. For TDX, though, the craziness is mostly hidden in the TDX module. > What else uses the S3M? Do we have to worry about contending with > non-TDX usage? There _are_ different users of S3M. But each of them should get their own I/O address and S3M firmware has to handle talking to those different users at the same time. The TDX I/O window is owned exclusively by the TDX module. So, while S3M has and long and growing list of jobs, the random software (like the host kernel) poking at one I/O window doesn't have to know about the other piece of software (the TDX module) poking at another. I'm sure I got a detail or two wrong in there, so folks that know this better: please correct me. But I think that's a halfway-decent 10,000ft view.